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參數(shù)資料
| 型號： | TMP141AIDBVTG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 662K |
| 描述： | IC TEMP SENSOR DGTL OUT SOT23-6 |
| 標準包裝： | 250 |
| 系列： | SensorPath™ |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內部 |
| 感應溫度： | -40°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓撲： | ADC（三角積分型），寄存器庫 |
| 輸出類型： | 1 線 SensorPath? |
| 輸出警報： | 無 |
| 輸出風扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
TMP141
SBAS347A MARCH 2005 REVISED JULY 2006
www.ti.com
14
EXCEPTION HANDLING
ATTENTION REQUEST
Two conditions can cause the TM141 to generate an
Attention Request: a conversion completion and a bus
error.
Upon completion of a conversion, an Attention Request
may be asserted if an Attention Request is enabled (bit 0
in the Temperature Control register), if the bus is inactive,
and if there has not been an Attention Request on the bus
since the Device Status register was last read or the last
bus reset.
A slave generates an Attention Request by holding the bus
low for time t
SLoutA
. Because it is longer than any other
signal (except Reset), it takes priority over the other bus
signals (Start, Data 1, and Data 0).
ATTENTION REQUEST SERVICE
The master is required to read the status register of all
slaves after an Attention Request to determine which
slave sent the request. While an Attention Request service
is pending, no slave can generate another Attention
Request to request a read of its Temperature Readout
register. However, Attention Requests caused by bus
errors will continue to be generated.
ACKNOWLEDGE (ACK)
During a Read transaction, the master sends the ACK bit
to indicate that the even parity (EP) bit was received, found
to be correct when compared to the data preceding it, and
no conflict was detected on the bus. During a Write
transaction, the slave sends the ACK bit with the same
meaning as when the master sends it. A transaction is
considered complete only when the ACK bit is received. If
an ACK bit of 1 is not received during a Write transaction,
the TMP141 will not perform any internal operations based
on that transaction. A transaction with an Acknowledge bit
of 0 is not considered complete by the TMP141, and the
following actions are performed:
1. The bus error bit in the TMP141 Device Status register
is set.
2. The TMP141 generates an Attention Request before
(or together with) the Start Bit of the next transaction.
A transaction that was not positively acknowledged is also
not considered complete by the master (that is, the master
will not use data that it received from a transaction that was
not acknowledged). The transaction may be repeated by
the master after detecting the source of the Attention
Request (the TMP141 or other slave that has a set BER bit
in the Device Status Register). Note that the SensorPath
protocol neither forces, nor automates re-execution of, the
transaction by the master.
Incomplete Transactions:
If the TMP141 receives a Start Bit during a transaction, it
aborts the current transaction, and begins a new one. This
process is not recommended, but is a legal operation. No
error will be generated.
If excess bits are received, the extra bits are ignored. The
TMP141 expects the parity (EP) and acknowledge (ACK)
bits in the usual places. However, in such cases, there is
usually a parity error, and the transaction is not
acknowledged. Error handling proceeds as described in
the Acknowledge section.
If insufficient bits are received, the TMP141 will wait
indefinitely for the missing bits. If the master starts a new
transaction before those bits are received, the TMP141
abandons the current transaction, and begins the new
transaction. No error is generated.
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