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參數(shù)資料
| 型號(hào)： | TM2SN64EPU |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 存儲(chǔ)器模塊 |
| 英文描述： | 2Mx64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (PC66) |
| 中文描述： | 2Mx64 位同步動(dòng)態(tài) RAM 模塊 (PC66) |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | TM2SN64EPU |
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TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAMMODULES
SMMS681 – AUGUST 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2SN64EPU (Continued)
BYTE
NO.
DESCRIPTION OF FUNCTION
TM2SN64EPU-12A
TM2SN64EPU-12
ITEM
DATA
ITEM
DATA
22
SDRAM device attributes: general
VDD tolerance =
(+10%)/(–5%).
Burst read/write,
precharge all,
auto precharge
1Eh
VDD tolerance =
(+10%),
Burst read/write,
precharge all,
auto precharge
0Eh
23
Minimum clock cycle time at CL = X – 1
tCK = 15 ns
tAC = 9 ns
N/A
F0h
tCK = 18 ns
tAC = 10 ns
N/A
30h
24
Maximum data-access time from clock at CL = X – 1
90h
A0h
25
Minimum clock cycle time at CL = X – 2
00h
00h
26
Maximum data-access time from clock at CL = X – 2
N/A
00h
N/A
00h
27
Minimum row precharge time
tRP = 30 ns
tRRD = 24 ns
tRCD = 30 ns
tRAS = 60 ns
16M Bytes
1Eh
tRP = 36 ns
tRRD = 24 ns
tRCD = 30 ns
tRAS = 72 ns
16M Bytes
24h
28
Minimum row-active to row-active delay
18h
18h
29
Minimum RAS-to-CAS delay
1Eh
1Eh
30
Minimum RAS pulse width
3Ch
48h
31
Density of each bank on module
04h
04h
32–61
Superset features (may be used in the future)
62
SPD revision
Rev. 1
01h
Rev. 1
01h
63
Checksum for byte 0–62
7
07h
89
59h
64–71
Manufacturer’s JEDEC ID code per JEP–106E
Manufacturing location
Manufacturer’s part number
Die revision code
PCB revision code
Manufacturing date
Assembly serial number
Manufacturer specific data
Vendor specific data
System integrator’s specific data
Open
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
97h
9700...00h
97h
9700...00h
72
TBD
TBD
73–90
TBD
TBD
91
TBD
TBD
92
TBD
TBD
93–94
TBD
TBD
95–98
TBD
TBD
99–125
TBD
TBD
126–127
TBD
TBD
128–166
TBD
TBD
167–255
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TM2SN64EPU-12 | SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SN64EPU-12A | SYNCHRONOUS DYNAMIC RAM MODULES |
| TMS3121 | QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS |
| TMS3121JC | QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS |
| TMS3121NC | QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TM2SN64EPU-12 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SN64EPU-12A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPH | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPU | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
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