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參數(shù)資料
| 型號： | TM2SN64EPU-12 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 存儲(chǔ)器模塊 |
| 英文描述： | SYNCHRONOUS DYNAMIC RAM MODULES |
| 中文描述： | 同步動(dòng)態(tài)RAM模塊 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 271K |
| 代理商： | TM2SN64EPU-12 |
TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAMMODULES
SMMS681 – AUGUST 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Organization:
– TM2SN64EPU . . . 2 097 152 x 64 Bits
– TM4SN64EPU . . . 4 194 304 x 64 Bits
Single 3.3-V Power Supply
(
±
10% Tolerance)
Designed for 66-MHz 4-Clock Systems
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
TM2SN64EPU — Uses Eight 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M
×
8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
TM4SN64EPU — Uses Sixteen 16M-Bit
SDRAMs (2M
×
8-Bit) in Plastic TSOPs
Byte-Read/Write Capability
Performance Ranges:
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Read Latencies 2 and 3 Supported
Support Burst-Interleave and
Burst-Interrupt Operations
Burst Length Programmable to 1, 2, 4,
and 8
Two Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0
°
C to 70
°
C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence-Detect (SPD) Using
EEPROM
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
(CL = 3)
ACCESS TIME
CLOCK TO
OUTPUT
tCK3
(CL = 3)
REFRESH
INTERVAL
tCK2
(CL = 2)
tCK2
(CL = 2)
’xSN64EPU-12A
12 ns
15 ns
9 ns
9 ns
64 ms
’xSN64EPU-12
CL = CAS latency
–12A speed device is supported only at –5 to +10% VDD
12 ns
18 ns
9 ns
10 ns
64 ms
description
The TM2SN64EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS626812DGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number
SMOS687).
The TM4SN64EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812DGE,
2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS626812 data sheet (literature number SMOS687).
operation
The TM2SN64EPU operates as eight TMS626812DGE devices that are connected as shown in the
TM2SN64EPU functional block diagram. The TM4SN64EPU operates as 16 TMS626812DGE devices
connected as shown in the TM4SN64EPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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| TMS3121JC | QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TM2SN64EPU-12A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPH | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2SR72EPU | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
| TM2TR64EPH | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SYNCHRONOUS DYNAMIC RAM MODULES |
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