TLV990-13
3-V, 10-BIT, 13-MSPS AREA CCD ANALOG FRONT END
SLAS282 – JULY 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
input blanking function
Large input transients may occur at the TLV990-13’s input during some period of operation which can saturate
the input circuits and cause long recovery time. To prevent circuit saturation the TLV990-13 includes an input
blanking function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulled
low. The TLV990-13 digital output will be set by the blanking data register after BLKG is pulled low.
NOTE:
If the BLKG pulse is located before the OBCLP pulse, there must be at least 4 pixels between the
rising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse is located
after the OBCLP, the minimum number of pixels between the falling edge of the OBCLP and the
falling edge of the BLKG pulse should be equal to the number of optical black pixels per line + 4.
3-wire serial interface
A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of
the TLV990-13. The serial clock SCLK can be run at a maximum frequency of 40 MHz. Serial data SDIN is 16
bits long. The two leading null bits are followed by four address bits for which the internal register is to be
updated, and then ten bits of data to be written to the register. The CS pin must be held low to enable the serial
port. The data transfer is initiated by the incoming SCLK after CS falls.
The SCLK polarity is selectable by pulling the SCKP pin either high or low.
device reset
When pin RESET (pin 29) is pulled low, all internal registers are set to their default values. The device also resets
itself when it is first powered on. In addition, the TLV990-13 has a software-reset function that resets the device
when writing a control bit to the control register.
See the
register definition section for the register default values.
voltage references
An internal precision-voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate
the ADC Ref– voltage of 1 V and Ref+ of 2 V. It is also used to set the clamp voltage. All internally-generated
voltages are fixed values and cannot be adjusted.
power-down mode (standby)
The TLV990-13 implements both hardware and software power-down modes. Pulling pin STBY (pin 30) low
puts the device in the low-power standby mode. Total supply current drops to about 0.6 mA. Setting a
power-down control bit in the control register can also activate the power-down mode. The user can still program
all internal registers during the power-down mode.
power supply
The TLV990-13 has several power-supply pins. Each major internal analog block has a dedicated AVDD supply
pin. All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3-V nominal.
The DIVDD and DIGND pins supply power to the output digital driver (D9–D0). The DIVDD is independent of the
DVDD and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiring
different supply voltages.