參數(shù)資料
型號(hào)： TLV5580PW
廠商： Texas Instruments, Inc.
英文描述： 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER
中文描述： 8位，80 MSPS的低功耗A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/34頁(yè)
文件大?。?/td> 531K
代理商： TLV5580PW
TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER
SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AIN
NO.
26
I
Analog input
AVDD
AVSS
BG
16, 27
I
Analog supply voltage
18, 23, 28
I
Analog ground
Band gap reference voltage. A 1
μ
F capacitor (with an optional 0.1
μ
F capacitor in parallel) should be
connected between this terminal and AVSS for external filtering.
Clock input. The input is sampled on each rising edge of CLK.
Common mode level. This voltage is equal to (AVDD – AVSS)
÷
2. An external 0.1
μ
F capacitor should be
connected between this terminal and AVSS.
Data outputs. D7 is the MSB
17
O
CLK
12
I
CML
25
O
D0 – D7
2 – 9
O
DRVDD
DRVSS
DVDD
OE
1
I
Supply voltage for digital output drivers
10
I
Ground for digital output drivers
14
I
Digital supply voltage
13
I
Output enable. When high the D0 – D7 outputs go in high-impedance mode.
DVSS
PWDN_REF
11
I
Digital ground
24
I
Power down for internal reference voltages. A high on this terminal will disable the internal reference
circuit.
REFBI
21
I
Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the
ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering
should be applied to this input. The use a 0.1
μ
F capacitor connected between REFBI and AVSS is
recommended. Additionaly, a 0.1
μ
F capacitor can be connected between REFTI and REFBI.
Reference voltage bottom output. An internally generated reference is available at this terminal. It can be
connected to REFBI or left unconnected. A 1
μ
F capacitor between REFBO and AVSS will provide
sufficient decoupling required for this output.
REFBO
22
O
REFTI
20
I
Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.
It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied to this input. The use of a 0.1
μ
F capacitor between REFTI and AVSS is recommended. Additionaly,
a 0.1
μ
F capacitor can be connected between REFTI and REFBI.
Reference voltage top output. An internally generated reference is available at this terminal. It can be
connected to REFTI or left unconnected. A 1
μ
F capacitor between REFTO and AVSS will provide sufficient
decoupling required for this output.
REFTO
19
O
STBY
15
I
Standby input. A high level on this input enables a powerdown mode.
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