參數(shù)資料
型號： TLV320DAC26IRHBR
英文描述： LOW POWER STEREO AUDIO DAC WITH HEADPHONE/SPEAKER AMPLIFIER
中文描述： 低功耗立體聲音頻DAC耳機/揚聲器放大器
文件頁數(shù)： 15/46頁
文件大?。?/td> 452K
代理商： TLV320DAC26IRHBR
SLAS428 AUGUST 2004
www.ti.com
15
I
2
S MODE
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of ADWS or
LRCK. Similarly the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of
LRCK.
BCLK
LRCK
DIN
n
n1
1
0
n
n1
1
0
LSB
MSB
n
1 clock before MSB
n2
2
n2
2
1/fs
Left Channel
Right Channel
Figure 11. Timing Diagram for I
2
S Mode
DSP MODE
In DSP mode, the falling edge of LRCK starts the data transfer with the left channel data first and immediately followed
by the right channel data. Each data bit is valid on the falling edge of BCLK.
BCLK
LRCK
DIN/
n
n1
1
0
n
n1
1
0
LSB
MSB
n
n1
1
0
MSB
LSB
n2
2
n2
2
n2
MSB
LSB
1/fs
Left Channel
Right Channel
Figure 12. Timing Diagram for DSP Mode
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