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參數(shù)資料
| 型號： | TLV320AIC33IRGZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Low Power Stereo Audio Codec for Portable Audio/Telephony |
| 中文描述： | 低功耗立體聲音頻編解碼器的便攜式音頻/電話 |
| 文件頁數(shù)： | 18/46頁 |
| 文件大?。?/td> | 452K |
| 代理商： | TLV320AIC33IRGZ |
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SLAS428 AUGUST 2004
www.ti.com
18
and implement a shelving filter with 0 dB gain from dc to approximately 150 Hz, at which point it rolls off to a 3-dB attenuation
for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented
by 16-bit twos complement numbers with values ranging from –32768 to +32767. Frequency response plots are given in
the
Audio DAC Filter Frequency Responses
section of this data sheet.
Interpolation Filter
The interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio. It
provides a linear phase output with a group delay of 21/Fs.
In addition, a digital interpolation filter provides enhanced image filtering and reduces signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples
of 8 kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc). The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener;
therefore, they must be filtered heavily to maintain good output quality. The interpolation filter is designed to maintain at
least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the programmable interpolation capability, the
Fsref should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use),
and the actual Fs is set using the dividers in bit D5D3/REG00H/Page2. For example, if Fs = 8 kHz is required, then Fsref
can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the 8-kHz data are sufficiently attenuated
well beyond the ~20-kHz audible frequency range.
Delta-Sigma DAC
The audio digital-to-analog converter incorporates a third order multibit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping
techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter followed by a continuous time RC
filter. The analog FIR operates at a rate of 128 x Fsref (6.144 MHz when Fsref = 48 kHz, 5.6448 MHz when Fsref = 44.1 kHz).
Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must
be taken to keep jitter on this clock to a minimum.
DAC Digital Volume Control
The DAC has a digital volume control block, which implements programmable gain. The volume level can be varied from
0 dB to –63.5 dB in 0.5 dB steps. In addition, there is an independent mute bit for each channel. The volume level of both
channels can also be changed simultaneously by the master volume control. The gain is implemented with a soft-stepping
algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume
is reached. The rate of soft-stepping can be slowed to one step per two input samples through bit D1 of control register
04H/Page2.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the
host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this
situation, the ’DAC26 provides a flag back to the host via a read-only register bit (D2D3 of control register 04H/Page2)
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume
level. The soft-stepping feature can be disabled by programming D14=1 in register 1DH in Page02. If soft-stepping is
enabled, the MCLK signal to the device should not be changed until the DAC power-down flag is set. When this flag is set,
the internal soft-stepping process and power-down sequence is complete, and the MCLK can be stopped if desired.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC33IRGZR | 功能描述:接口—CODEC Low-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC33IRGZR | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC ((NW)) 制造商:Texas Instruments 功能描述:IC, AUDIO CODEC, 24BIT, 96KHZ, QFN-48 |
| TLV320AIC33IRGZRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC33IRGZT | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC33IRGZT | 制造商:Texas Instruments 功能描述:IC STEREO AUDIO CODEC 48-VQFN |
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