參數(shù)資料
型號： TLV320AIC3107YZFR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 2 CHANNEL, AUDIO AMPLIFIER, PBGA42
封裝： 3.50 X 3 MM, 0.50 MM PITCH, WSCP-42
文件頁數(shù)： 79/94頁
文件大小： 1183K
代理商： TLV320AIC3107YZFR
SLOS545B – NOVEMBER 2008 – REVISED JANUARY 2009........................................................................................................................................... www.ti.com
Page 0 / Register 106:
Right AGC New Programmable Decay Time Register(1)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Decay Time Register Selection
0: Decay time for the Right AGC is generated from Register 29.
1: Decay time for the Right AGC is generated from this Register.
D6-D5
R/W
00
Baseline AGC Decay time
00: Right AGC Decay time = 50-msec
01: Right AGC Decay time = 150-msec
10: Right AGC Decay time = 250-msec
11: Right AGC Decay time = 350-msec
D4-D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC Decay time = 1
001: Multiplication factor for the baseline AGC Decay time = 2
010: Multiplication factor for the baseline AGC Decay time = 4
011: Multiplication factor for the baseline AGC Decay time = 8
100: Multiplication factor for the baseline AGC Decay time = 16
101: Multiplication factor for the baseline AGC Decay time = 32
110: Multiplication factor for the baseline AGC Decay time = 64
111: Multiplication factor for the baseline AGC Decay time = 128
D1-D0
R/W
00
Reserved. Write only zero to these register bits.
(1)
Decay time is limited based on NADC ratio that is selected. For
NADC = 1, Max Decay time = 4 seconds
NADC = 1.5, Max Decay time = 5.6 seconds
NADC = 2, Max Decay time = 8 seconds
NADC = 2.5, Max Decay time = 9.6 seconds
NADC = 3 or 3.5, Max Decay time = 11.2 seconds
NADC = 4 or 4.5, Max Decay time = 16 seconds
NADC = 5, Max Decay time = 19.2 seconds
NADC = 5.5 or 6, Max Decay time = 22.4 seconds
Page 0 / Register 107:
New Programmable ADC Digital Path and I2C Bus Condition Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Left Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
D6
R/W
0
Right Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
D5-D4
R/W
00
Reserved. Write only zeroes to these bits.
D3
R/W
0
ADC Digital output to Programmable Filter Path Selection
0: No additional Programmable Filters other than the HPF are used for the ADC.
1: The Programmable Filter is connected to ADC output, if both DACs are powered down.
D2
R/W
0
I2C Bus Condition Detector
0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I2C bus error.
D1
R
0
Reserved. Write only zero to these register bits.
D0
R
0
I2C Bus error detection status
0: I2C bus error is not detected
1: I2C bus error is detected. This bit is cleared by reading this register.
80
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3107
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