參數(shù)資料
型號： TLV320AIC3107YZFR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 2 CHANNEL, AUDIO AMPLIFIER, PBGA42
封裝： 3.50 X 3 MM, 0.50 MM PITCH, WSCP-42
文件頁數(shù)： 71/94頁
文件大?。?/td> 1183K
代理商： TLV320AIC3107YZFR
www.ti.com........................................................................................................................................... SLOS545B – NOVEMBER 2008 – REVISED JANUARY 2009
Page 0 / Register 86:
LEFT_LOP Output Level Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
LEFT_LOP Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
LEFT_LOP Mute
0: LEFT_LOP is muted
1: LEFT_LOP is not muted
D2
R
0
Reserved. Don’t write to this register bit.
D1
R
1
LEFT_LOP Volume Control Status
0: All programmed gains to LEFT_LOP have been applied
1: Not all programmed gains to LEFT_LOP have been applied yet
D0
R
0
LEFT_LOP Power Status
0: LEFT_LOP is not fully powered up
1: LEFT_LOP is fully powered up
Page 0 / Register 87:
LINE2L to RIGHT_LOP Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to RIGHT_LOP
1: LINE2L is routed to RIGHT_LOP
D6-D0
R/W
0000000
LINE2L to RIGHT_LOP Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 88:
PGA_L to RIGHT_LOP Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP
1: PGA_L is routed to RIGHT_LOP
D6-D0
R/W
0000000
PGA_L to RIGHT_LOP Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 89:
DAC_L1 to RIGHT_LOP Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP
1: DAC_L1 is routed to RIGHT_LOP
D6-D0
R/W
0000000
DAC_L1 to RIGHT_LOP Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Page 0 / Register 90:
LINE2R to RIGHT_LOP Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to RIGHT_LOP
1: LINE2R is routed to RIGHT_LOP
D6-D0
R/W
0000000
LINE2R to RIGHT_LOP Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5
Copyright 2008–2009, Texas Instruments Incorporated
73
Product Folder Link(s): TLV320AIC3107
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