參數(shù)資料
型號(hào)： TLV320AIC29IRGZTG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁(yè)數(shù)： 37/87頁(yè)
文件大?。?/td> 1051K
代理商： TLV320AIC29IRGZTG4
TLV320AIC29
SLAS494B DECEMBER 2005 REVISED OCTOBER 2007
www.ti.com
42
AIC29 COMMUNICATION PROTOCOL
Register Programming
The AIC29 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI master
and accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command
is constructed as shown in Figure 32.
The command word begins with an R/W bit, which specifies the direction of data flow on the SPI serial bus. The
following 4 bits specify the page of memory this command is directed to, as shown in Table 4. The next six bits
specify the register address on that page of memory to which the data is directed. The last five bits are reserved
for future use and should be written only with zeros.
Table 4. Page Addressing
PG3
PG2
PG1
PG0
PAGE ADDRESSED
0
1
0
1
0
2
0
1
3
0
1
0
Reserved
0
1
0
1
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
To read all the first page of memory, for example, the host processor must send the AIC29 the command 0x8000
– this specifies a read operation beginning at page 0, address 0. The processor can then start clocking data
out of the AIC29. The AIC29 automatically increments its address pointer to the end of the page; if the host
processor continues clocking data out past the end of a page, the AIC29 sends back the value 0xFFFF.
Likewise, writing to page 1 of memory would consist of the processor writing the command 0x0800, which
specifies a write operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointer
pointing at the first location in memory on page 1. See the section on the AIC29 memory map for details of
register locations.
BIT 15
MSB
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
R/W*
PG3
PG2
PG1
PG0
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
0
Figure 32. AIC29 Command Word
COMMAND WORD
DATA
SS
SCLK
MOSI
Figure 33. Register Write Opration
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