參數(shù)資料
型號(hào)： TLV320AIC29IRGZTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁(yè)數(shù)： 28/87頁(yè)
文件大?。?/td> 1051K
代理商： TLV320AIC29IRGZTG4
TLV320AIC29
SLAS494B DECEMBER 2005 REVISED OCTOBER 2007
www.ti.com
34
Differential Smart Phone Interface
The TLV320AIC29 provides a pincompatible upgrade to TLV320AIC28. One improvement is the ability to
connect diferentially to a cell phone module, which improves noise immunity in the customers system. When
configured as differential input (bit D10, Register 06h) the CP_INP pin and BUZZ_IN/CP_INN pin function as
a differential input to the CP_INP PGA. In this mode, the gain of the CP_IN PGA is increased by +6 dB over
the default mode, so the PGA gain range is 28.5 dB to +18 dB. Also, in differential input mode, BUZZ_IN must
be disconnected from the BUZZ_IN PGA (bit D8, Register 25h, page 2).
When configured as differential output (bit D9, Register 06h, page 2), the CP_OUTP and VGND/CP_OUTN
pins function as a differential output pair. This differential output will only allow the signal on MICSEL (bits
D7D5, Register 03h, page 2) to be routed out. When differential mode is used, capless headphone output must
be disabled (bit D3, Register 21h, page 2) and VGND msut be powered down (bit D8, Register 05h, page 2).
DAC Headphone Pop Reduction
The TLV320AIC29 contains circuitry to reduce the level of ’pop noise’ heard when connecting the DAC to the
headphone outputs. This mode is valid only for DAC to headphone (SPK1/2) routing. DAC pop removal should
be enabled (bit D9, Register 21H, page2) before turning on the DAC. This bit should also be disabled just before
turning off the DAC.
This Pop reduction mode is not valid for DAC to speaker driver routing, so this mode must be disabled in all
other cases. It is automatically disabled for DAC to SPK1OUT32N routing. When a signal other than the DAC
is already selected for headphone driver (SPK1/2) and then DAC to SPK1/2 routing is desired, then this scheme
should be disabled.
Analog Mixer
The analog mixer can be used to route the analog input selected for the ADC through an analog volume control
and then mix it with the audio DAC output. The analog mixer feature is available only if the single ended
microphone input or the AUX input is selected as the input to the ADC, not when the ADC input is configured
in fully-differential mode. This feature is available even if the ADC and DAC are powered down. The analog
volume control has a range from +12 dB to –34.5 dB in 0.5 dB steps plus mute and includes softstepping logic.
The internal oscillator is used for softstepping whenever the ADC and DAC are powered down.
Keyclick
A special circuit has been included for inserting a squarewave signal into the analog output signal path based
on register control. This functionality is intended for generating keyclick sounds for user feedback. Register
04H/Page 2 contains bits that control the amplitude, frequency, and duration of the squarewave signal. The
frequency of the signal can be varied from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periods
to 32 periods. Whenever this register is written, the square wave is generated and coupled into the audio output.
The keyclick enable bit D15 of control register 04H/Page 2 is reset after the duration of a keyclick is played out.
This capability is available even when the ADC and DAC are powered down.
OPERATION—AUXILIARY MEASUREMENT
Auxiliary ADC Converter
The auxiliary analog inputs (battery voltage monitor, chip temperature, and auxiliary inputs) are provided via
a multiplexer to the successive approximation register (SAR) analog-to-digital (A/D) converter. The ADC
architecture is based on capacitive redistribution architecture, which inherently includes a sample/hold function.
The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon
the bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate
may all be programmed through this register. These modes are outlined in the sections below for each type of
analog input. The results of conversions made are stored in the appropriate result register.
Data Format
The AIC29 output data is in unsigned Binary format and can be read from registers over the SPI interface.
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