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| 型號： | TLV2544EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT ADC EVALUATION MODULE(12位ADC評估板) |
| 中文描述： | 12位ADC評估板（12位ADC的評估板） |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 775K |
| 代理商： | TLV2544EVM |
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ADC EVM Operational Procedure
1-5
Overview
1.6
ADC EVM Operational Procedure
Some signal setup or software is required for the ADC EVM. The ADC data
sheet (refer to section 4.3 for specific ADC data sheet information) provides
the timing requirements and the application report (literature number
SLAA025A and SLAA028A) supplies an example of software using the
TMS320C50 DSP and TMS320C203 DSP. Once the input requirements are
completed, the operating procedures for the ADC EVM are as follows.
Connect
±
7 to
±
10 V and ground to the 10 V, –10 V, and GND terminals
of J10. These terminals are marked on the top side of the EVM silkscreen.
TP3–TP8 is shorted to establish zero volts as the operating point. When
TP1 and TP2 are shorted, the output at both the TLV2772 and TLE2142
operational amplifiers, reads 2.5 V for an AVDD of 5 V.
SW1 can select 5-V V
CC
or 3.3-V V
CC
, making it convenient to evaluate
both 3.3-V and 5-V systems. Note that when evaluating the TLC version
the switch, SW1, is not installed as discussed in section 1.2.
For most DSP operation, JP1 is open, and for most microprocessor
operation, JP1 is shorted. The device INV CLK/ PWDN input is controlled
by this jumper. The state of the inverted signal is used to control the I/O
CLK edge used for sampling the input data. Applying a logic low signal to
the PWDN causes both analog and digital circuits to go into the
power-down mode.
The analog input that is connected to the ADC is determined by software,
and any input can be selected for testing. The TLV1544/2544 and
TLC1514/2554 four channels are configured as follows:
Analog Input
A0
Interface to a buffer driven by a single supply input scaling
operational amplifier
Unbuffered external input is via W2 positions 1–2
A1
Interface to a buffer driven by a dual supply,
±
10 V used for
input scaling
Unbuffered external input is provided via W1 positions 1–2
A2
Uses unbuffered external input
A3
Uses unbuffered external input or dc REF_CH3/7
A4–A7 Uses unbuffered external input
Normally, through the software, or loopback testing via the TLC5618A, the
ADC full-scale, mid-scale, and zero-scale values are first checked. Chan-
nel A3/A7 can be selected and checked with the dc signal REF_CH3/7 us-
ing jumper W3.
An external reference voltage, derived from a MAX6250 precision voltage
regulator, is used to provide the REF+ and REF– reference voltage for the
ADC as well as the 2.5 V reference for the TLC5618A – when operating
the ADC with
Vref = 5 V.
Designation Reference Voltage
Onboard absolute reference = 5 V, at Vin = 7 V to 10 V
When SW1 is changed the onboard absolute reference is automatically
changed to the proper value for the DVdd/AVdd selected.
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| TLV2544IDR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2544IDRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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