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參數資料
| 型號： | TLV2354IPWRG4 |
| 廠商： | Texas Instruments |
| 文件頁數： | 4/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIFF COMPARATOR QUAD 14-TSSOP |
| 標準包裝： | 2,000 |
| 系列： | LinCMOS™ |
| 類型： | 差分 |
| 元件數： | 4 |
| 輸出類型： | CMOS，MOS，開路漏極，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2 V ~ 8 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 5pA @ 5V |
| 電流 - 輸出（標準）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 800µA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
TLV2354, TLV2354Y
LinCMOS
QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
–
+
DUT
VDD
+
–
+
–
+
C2
1
F
R4
47 k
R5
1.8 k
, 1%
C3
0.68
F
U1c 1/4
TLV2354
U1b 1/4
TLV2354
U1a 1/4
TLV2354
R7
1 M
R8
1.8 k
, 1%
R9
10 k
, 1%
R1
240 k
R2
10 k
C1
0.1
F
R3
100
C4
0.1
F
Integrator
R10
100
, 1%
Buffer
Triangle
Generator
VIO
(
×100)
R6
5.1 k
Figure 10. Circuit for Input Offset Voltage Measurement
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