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參數(shù)資料
| 型號(hào)： | TLE6209R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 7 A, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOP-20 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 323K |
| 代理商： | TLE6209R |
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TLE 6209 R
Data Sheet, Version 3.1
3
2007-08-01
1.2.1
Pin No. Symbol Function
1, 10,
11, 20
2,3
OUT1
Pin Definitions and Functions
GND
Ground;
internally connected to cooling tab (heat slug); to reduce
thermal resistance place cooling areas and thermal vias on PCB.
Output 1
; output of D-MOS half bridge 1; external connection
between pin 2 and pin 3 is necessary.
Power supply
; needs a blocking capacitor as close as possible to
GND; 47
μ
F electrolytic in parallel to 220 nF ceramic is
recommended; external connection between pin 4 and pin 17 is
necessary.
Serial clock input
; clocks the shiftregister; SCLK has an internal
active pull down and requires CMOS logic levels
Serial data input;
receives serial data from the control device;
serial data transmitted to SDI is an 8 bit control word with the Least
Significant Bit (LSB) being transferred first; the input has an active
pull down and requires CMOS logic levels; SDI will accept data on
the falling edge of SCLK-signal; see
Table 1
for input data protocol.
Serial-Data-Output;
this tri-state output transfers diagnosis data to
the control device; the output will remain tri-stated unless the device
is selected by a low on Chip-Select-Not (CSN); SDO state changes
on the rising edge of SCLK; see
Table 4
for diagnosis protocol.
Chip-Select-Not input
; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when SCLK is low; CSN has an
internal active pull up and requires CMOS logic levels.
Inhibit input;
has an internal pull down; device is switched in
standby condition by pulling the INH terminal low.
Disable input;
has an internal pull up; the output stages are
switched in tristate condition by pulling the DIS terminal high.
Direction input;
has an internal pull down; TTL/CMOS compatible
input.
PWM input;
has an internal pull down; TTL/CMOS compatible
input.
Logic supply voltage
; needs a blocking capacitor as close as
possible to GND; 10
μ
F electrolytic in parallel to 220 nF ceramic is
recommended.
4,17
V
S
5
SCLK
6
SDI
7
SDO
8
CSN
9
INH
12
DIS
13
DIR
14
PWM
15
V
CC
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