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參數(shù)資料
| 型號： | TLC876MDW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 10位20 MSPS的并行輸出CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 314K |
| 代理商： | TLC876MDW |
TLC876M TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140D – JULY 1997 – REVISED MAY 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics at AV
DD
= DV
DD
= 5 V, DRV
DD
= 3.3 V, V
I(REFT)
= 3.6 V, V
I(REFB)
= 1.6 V,
f
CLK
= 20 MSPS (unless otherwise noted)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
±
1.5
±
0.5
–0.4
MAX
UNIT
Integral nonlinearity (INL)
LSB
Differential nonlinearity (DNL) (see Note 1)
<
±
1
Offset error
%FSR
Gain error
0.2
%FSR
NOTE 1: A differential nonlinearity error of less than
±
1 LSB ensures no missing codes.
analog input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ci
Input capacitance
5
pF
reference input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
Rref
Iref
Reference input resistance
350
500
750
Reference input current
4
Reference top offset voltage
35
mV
Reference bottom offset voltage
35
mV
dynamic performance
PARAMETER
TEST CONDITIONS
fI = 1 MHz
fI = 3.58 MHz,
TA = 25
°
C
MIN
TYP
8.5
MAX
UNIT
All suffixes
Effective number of bits (ENOB)
f bit (ENOB)
All suffixes
8
8.5
Bits
C and I suffixes
fI = 3.58 MHz,
TA = Full Range
fI = 10 MHz
fI = 1 MHz
fI = 3.58 MHz,
TA = 25
°
C
8
8.5
M suffix
7.5
All suffixes
8.1
All suffixes
53
Signal-to-total harmonic distortion+noise
Signal to total harmonic distortion+noise
(S/(THD+N))
All suffixes
50
53
dB
C and I suffixes
fI = 3.58 MHz,
TA = Full Range
fI = 10 MHz
fI = 1 MHz
fI = 3.58 MHz
fI = 10 MHz
fI = 3.58 MHz
50
53
M suffix
47
All suffixes
51
–63
Total harmonic distortion (THD)
–62
–56
dB
–61
Spurious free dynamic range
–64
dB
BW
Analog input full-power bandwidth
200
MHz
Differential phase
0.5
degrees
Differential gain
1%
The voltage difference between AVDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At input clock rise times less than
20 ns, the offset full-scale error increases approximately by a factor of (20/tr)0.5 where tr equals the actual rise time in nanoseconds.
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