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參數資料
| 型號： | tlc320ad56c |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路) |
| 中文描述： | sigma - delta模擬接口電路（Σ-Δ模擬接口電路） |
| 文件頁數： | 11/38頁 |
| 文件大?。?/td> | 253K |
| 代理商： | TLC320AD56C |
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1–6
1.5
Terminal Functions (Continued)
TERMINALS
I/O
DESCRIPTION
NAME
NUMBER
PT
FN
OUTP
1
5
O
Noninverting current output of the DAC. OUTM and OUTP current outputs can
be loaded with 5 k
differentially or single ended. This signal can also be used
alone for single-ended operation.
PWRDWN
6
8
I
Power down. When this terminal is pulled low, the device goes into a power-down
mode; the serial interface is disabled and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when this terminal is pulled high
again. PWRDWN resets the counters only and preserves the programmed
register contents. See subsection 2.21. Reset and Power-Down Functions.
RESET
7
9
I
Reset. The reset function is provided to initialize all the internal registers to their
default values. The serial port can be configured to the default state accordingly.
Refer to section 1.7 Register Functional Summaryand subsection 2.2.1 Reset
and Power-Down Functionsfor more detailed descriptions.
SCLK
16
14
O
Shift clock. The shift clock signal is derived from MCLK and is used to clock serial
data into DIN and out of DOUT.
VSS(SUB)
VCOM(ADC)
30
22
I
Analog substrate. This terminal must be grounded.
46
2
O
Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10
μ
F. This node should be loaded only with a high-impedance dc load.
Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10
μ
F. This node should be loaded only with a high-impedance dc load.
Analog ground
VCOM(DAC)
4
7
O
AVSS
28
21
I
NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.
1.6
Definitions and Terminology
Data Transfer Interval
This is time during which data is transferred from DOUT and to DIN. This interval
is 16 shift clocks and this data transfer is initiated by the falling edge of the
frame-sync signal.
Signal Data
This refers to the input signal and all of the converted representations through the
ADC channel and return through the DAC channel to the analog output. This is
contrasted with the purely digital software control data.
Primary
Communications
This refers to the digital data transfer interval. Since the device is synchronous, the
signal data words from the ADC channel and to the DAC channel occur
simultaneously.
Secondary
Communications
This refers to the digital control and configuration data transfer interval into DIN and
the register read data cycle from DOUT. The data transfer interval occurs when
requested by hardware or software.
Frame Sync
Frame sync refers only to the falling edge of the signal that initiates the data transfer
interval. The primary frame sync starts the primary communications, and the
secondary frame sync starts the secondary communications.
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相關代理商/技術參數 |
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| TLC320AD56CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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| TLC320AD57 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD57C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD57CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
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