參數(shù)資料
型號： tlc320ad56c
廠商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
中文描述： sigma - delta模擬接口電路（Σ-Δ模擬接口電路）
文件頁數(shù)： 10/38頁
文件大?。?/td> 253K
代理商： TLC320AD56C
1–5
1.5
Terminal Functions
TERMINALS
NUMBER
PT
I/O
DESCRIPTION
NAME
FN
ALT DATA
25
19
I
Signals on this terminal are routed to DOUT during secondary communication
if phone mode is enabled.
AUXM
38
26
I
Inverting input to auxiliary analog input. AUXM requires an external RC antialias
filter.
AUXP
39
27
I
Noninverting input to auxiliary analog input. Requires an external RC antialias
filter.
AVDD
33
23
I
Analog ADC path supply (5 V only)
DIN
10
11
I
Data input. DIN receives the DAC input data and command information from the
DSP and is synchronized to SCLK.
DOUT
12
12
O
Data output. DOUT transmits the ADC output bits and is synchronized to SCLK.
This terminal is at high-Z when FS is not activated.
DVDD
DVSS
9
10
I
Digital power supply (5 V or 3 V)
26
20
I
Digital ground
FC
21
16
I
Function code. FC is sampled and latched on the rising edge of FS for the primary
serial communication. Refer to the Serial Communications section for more
details.
FLAG 0
23
17
O
Output flag 0. During phone mode, FLAG 0 contains the value set in Control 2
register.
FLAG 1
24
18
O
Output flag 1. During phone mode, FLAG 1 contains the value set in Control 2
register.
FILT
47
3
O
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
provides 2.5 V to which the analog inputs or outputs can be referenced. The
optimal capacitor value is 0.1
μ
F (ceramic). This voltage node should be loaded
only with a high-impedance dc load.
FS
13
13
O
Frame sync. When FS goes low, the serial communication port is activated. In
all serial transmission modes, FS is held low during bit transmission. Refer to
section 3 Serial Communicationsfor detailed description.
INM
36
25
I
Inverting input to analog modulator. INM requires an external RC antialias filter.
INP
35
24
I
Noninverting input to analog modulator. INP requires an external RC antialias
filter.
IGAIN
45
1
O
Current gain reference scaling. IGAIN is provided for decoupling of the current
gain reference and provides a 1.35-V reference. The optimal load is a
27-K resistor.
MCLK
17
15
I
Master clock. The master clock derives the internal clocks of the sigma-delta
analog interface circuit.
MONOUT
40
28
O
Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using Control 2 register.
OUTM
2
6
O
Inverting current output of the DAC. OUTM is functionally identical with and
complementary to OUTP. OUTM and OUTP current outputs can be loaded with
5 k
differentially or single-ended. This signal can also be used alone for
single-ended operation.
NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
TLC320AD56CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
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TLC320AD57 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD57C 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD57CDW 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
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