參數(shù)資料
型號： TLC320AD50IPT
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： PLASTIC, QFP-48
文件頁數(shù)： 32/52頁
文件大?。?/td> 276K
代理商： TLC320AD50IPT
4–5
4.3.8
DAC Channel Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic range
88
dB
Interchannel isolation
100
dB
EG
Gain error, 0 dB
VO = 0 dB at 1020 Hz
±0.3
dB
Idle channel narrow band noise
0 – 4 kHz,
See Note 7
125
V rms
VOO
Output offset voltage at OUT (differential)
DIN = All 0s
30
mV
VO
Analog output voltage, OUTP – OUTM
RL = 600 typ
(see Figure 3–8) with internal reference
and full-scale digital input,
See Note 8, differential
6
VPP
Total out of band energy (0.55 fs to 3 MHz)
–45
dB
Channel delay
18/fs
NOTES:
7. The conversion rate is 8 kHz; the-out-of-band measurement is made from 4400 Hz to 3 MHz.
8. The digital input to the DAC channel at DIN is in 2s complement format. The TLC320AD50C/52C DAC is of the voltage-type and
requires a load resistor for current to voltage conversion.
4.3.9
Power Supply, AVDD = DVDD = 5 V, No Load
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD (analog)
Power supply current ADC
Operating
18
24
mA
IDD (analog)
Power supply current, ADC
Power down
1
mA
IDD (PLL)
Power supply current PLL
Operating
2
4
mA
IDD (PLL)
Power supply current, PLL
Power down
0.5
mA
IDD (digital 1) Power supply current digital
Operating
4
6
mA
IDD (digital 1) Power supply current, digital
Power down
10
A
IDD (digital 2) Power supply current digital DVDD =3V
Operating
4
mA
IDD (digital 2) Power supply current, digital, DVDD = 3 V
Power down
10
A
PD
Power dissipation
Operating
120
170
mW
PD
Power dissi ation
H/W-power down
7.5
20
mW
4.3.10 Power-Supply Rejection, AVDD = DVDD = 5 V (see Note 9)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
Supply voltage rejection ratio, analog supply
fj = 0 to fs/2
50
DVDD
Supply voltage rejection ratio, DAC channel
fj = 0 to 30 kHz
40
dB
DVDD
Supply voltage rejection ratio, ADC channel
fj = 0 to 30 kHz
50
NOTE 9: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV peak-to-peak signal
applied to the appropriate supply.
4.4
Timing Characteristics (see Parameter Measurement Information)
4.4.1
Master Mode Timing Requirements
MIN
NOM
MAX
UNIT
td1
Delay time, SCLK
↑ to FS↓
0
tsu1
Setup time, DIN, before SCLK low
25
th1
Hold time, DIN, after SCLK low
20
ns
td(CH–FDL) Delay time, SCLK high to FSD low (see Figure 5–1)
50
ns
twH
Pulse duration, MCLK high
32
twL
Pulse duration, MCLK low
20
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