參數(shù)資料
型號： TLC320AD50IPT
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： PLASTIC, QFP-48
文件頁數(shù)： 17/52頁
文件大小： 276K
代理商： TLC320AD50IPT
2–9
2.7.3
Frame-Sync Delayed (FSD) Function, Master Mode
The timing relationships are as follows:
When the FSD register (control 3 register) data is 0 (default state at power up), then FSD goes low 1/4 SCLK
prior to the rising edge of SCLK when FS goes low (Figure 2–10).
When the FSD register data is greater than 17, then FSD goes low on the rising edge of SCLK that is the
FSD register number of SCLKs after the falling edge of FS (Figure 2–11).
Register data values from 1 to 17 result in a default register value of zero and should not be used.
SCLK
MP and SP
See Note A
FSD
(P and S)
See Note B
FS (P)
See Note B
FSD (P)
See Note B
MS and SS
See Note A
FS
(P and S)
See Note B
NOTES: A. The DIN of master and slave devices share the same DIN bus during first initialization. The DOUT is occupied by the Master device
only until the control 3 register of master and slave device is programmed with slave devices number and number of SCLKs between
FS and FSD (m>17).
B. P&S: Primary and secondary communications P: Primary communication only
Figure 2–10. Master Device FS and FSD Output When FSD Register (D0–D5, Control 3 Register) is 0
FS
FSD
256 SCLKs
MP
SP
MS
SS
MP
128 SCLKs
Delay is
m
SCLKs (
m > 17)
NOTES: A. Since master and slave share the same DIN bus during first initialization, they share the same input data word. Only one write cycle
is needed to program control 3 register of master device and slave device(s).
B. After the control 3 register is programmed, the DIN or DOUT bus of master and slave(s) are separated by time, although they still
physically connect to each other.
Figure 2–11. Master Device FS and FSD Output After Control 3 Register Is Programmed
(One Slave Device)
2.7.4
Frame-Sync Delayed (FSD), Slave Mode
The master FSD is output to the first slave device and the first slave FSD is output to the second slave device and
so on (see Figure 2–12). The FSD output of each device is input to the FS terminal of the succeeding device. The
FSD timing sequence in the slave mode is as follows:
When the FSD register data is 0, then FSD goes low 1/4 SCLK cycle before FS goes low.
When the FSD register data is greater than 17, then FSD goes low on the rising edge of the SCLK that is
equal to the FSD register number of SCLKs after the falling edge of FS (see Figure 2–13).
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