- 您現在的位置：買賣IC網 > PDF目錄383954 > TLC320AD50IPT (Texas Instruments, Inc.) SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION PDF資料下載
參數資料
| 型號： | TLC320AD50IPT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| 中文描述： | sigma - delta模擬接口，具有大師電路，從功能 |
| 文件頁數： | 24/84頁 |
| 文件大?。?/td> | 447K |
| 代理商： | TLC320AD50IPT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
2–9
2.9
2.9.1
The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11:
Operating Frequencies
Master and Stand-Alone Operating Frequencies
fs
Sampling (conversion) frequency
MCLK
(B register value)
(A register value)
2
(11)
The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SCLK) frequency is given in equation 12:
MCLK frequency
4
2.9.2
Slave and Codec Operating Frequencies
The slave operating frequencies are either the default values or programmed by the control data word from
the master and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.
2.10 Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by equation 13:
MCLK
(A register value)
2
2.11 Filter Bandwidths
The low-pass (LP) filter –3 dB corner is derived in equation 14:
FCLK
40
40
(A register value)
SCLK frequency
(12)
FCLK
(13)
f (LP)
MCLK
2
(14)
The high-pass (HP) filter –3 dB corner is derived in equation 15:
Sampling frequency
200
2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are
derived from the input master clock.The master clock applied at the MCLK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync
occurs approximately 648 master clocks after the reset condition disappears.
2.12.1
Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
f (HP)
MCLK
200
2
(A register value)
(B register value)
(15)
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back
相關PDF資料 |
PDF描述 |
|---|---|
| TLC320AD50(中文) | Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能) |
| TLC34075A-110 | Color-Palette(110MHz,視頻接口調色器) |
| TLC34075A-135 | Color-Palette(135MHz,視頻接口調色器) |
| TLC34075A-66 | Color-Palette(66MHz,視頻接口調色器) |
| TLC34075A-85 | Color-Palette(85MHz,視頻接口調色器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLC320AD52CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:PCM 數據接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數量:1 / 1 三角積分調變:是 S/N 比，標準 ADC / DAC (db):- 動態(tài)范圍，標準 ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應商設備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C-I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
發(fā)布緊急采購，3分鐘左右您將得到回復。