參數(shù)資料
型號(hào): TLC32046I
廠商: Texas Instruments, Inc.
英文描述: Wide-Band Analog Interface Circuit
中文描述: 寬帶模擬接口電路
文件頁數(shù): 36/57頁
文件大?。?/td> 297K
代理商: TLC32046I
3–6
3.4
Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, V
CC+
= 5 V, V
CC–
= –5 V, V
DD
= 5 V
Receive and Transmit Noise (measurement includes low-pass and band-pass
switched-capacitor filters)
PARAMETER
TEST CONDITIONS
Broadband with (sin x)/x
Broadband without (sin x)/x
0 to 30 kHz with (sin x)/x
0 to 30 kHz without (sin x)/x
0 to 3.4 kHz with (sin x)/x
Transmit
Constant input code
noise
0 to 6.8 kHz with (sin x)/x
(wide-band operation with 7.2 kHz
roll-off)
0 to 6.8 kHz without (sin x)/x
(wide-band operation with 7.2 kHz
roll-off)
3.4.1
MIN
TYP
250
200
200
200
180
160
MAX
500
450
400
400
300
300
UNIT
0 to 3.4 kHz without (sin x)/x
DX input = 00000000000000,
Constant in ut code
Vrms
μ
180
350
160
350
Receive noise (see Note 10)
Inputs grounded
In uts grounded,
Gain = 1
300
18
500
μ
Vrms
dBrnc0
All typical values are at TA = 25
°
C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the A/D converter.
3.5
3.5.1
Timing Requirements
Serial Port Recommended Input Signals, TLC32046C and TLC32046I
PARAMETER
MIN
MAX
UNIT
tc(MCLK)
tr(MCLK)
tf(MCLK)
Master clock cycle time
95
ns
Master clock rise time
10
ns
Master clock fall time
10
ns
Master clock duty cycle
25%
75%
RESET pulse duration (see Note 11)
DX setup time before SCLK
DX hold time after SCLK
800
ns
tsu(DX)
th(DX)
NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
20
ns
tc(SCLK)/4
ns
3.5.2
Serial Port Recommended Input Signals, TLC32046M
PARAMETER
MIN
TYP
MAX
UNIT
tc(MCLK)
tr(MCLK)
tf(MCLK)
Master clock cycle time
95
ns
Master clock rise time
10
ns
Master clock fall time
10
ns
Master clock duty cycle
50%
RESET pulse duration (see Note 11)
DX setup time before SCLK
DX hold time after SCLK
800
ns
tsu(DX)
th(DX)
NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
28
ns
tc(SCLK)/4
ns
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