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參數(shù)資料
| 型號： | TLC2942IDBLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 20 MHz, PDSO38 |
| 封裝： | PLASTIC, SO-38 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 473K |
| 代理商： | TLC2942IDBLE |
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The Kp
and KV values are obtained from the operating
characteristics of the device as shown in Figure
24. Kp is defined from the phase detector VOL and
VOH specifications and the equation shown in
Figure 24(b). KV is defined from Figures 8, 9, 10,
and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCOIN terminal. However,
for optimum temperature performance, a resistor value of 3.3 k
with a 3-V supply, or a resistor value of
2.5 k
for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice,
but a carbon-compositiion resistor can be used with excellent results also. A 0.22-
F capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
Dw
H ]
0.8 Kp
K
V
K
f
(
R)
Where
Kf (∞) = the filter transfer function value at ω = ∞
(1)
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2942
fREF
VOH
fMAX
fMIN
VIN MIN
VIN MAX
–2
π
2
π
–
π
0
π
Range of
Comparison
VOH
VOL
Kp =
VOH – VOL
4
π
KV =
2
π(fMAX – fMIN)
VIN MAX – VIN MIN
Figure 24. Example of a PLL Block Diagram
(a)
(c)
(b)
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