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參數(shù)資料
| 型號(hào)： | TLC2933IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 30 MHz, PDSO14 |
| 封裝： | PLASTIC, SO-14 |
| 文件頁(yè)數(shù)： | 21/23頁(yè) |
| 文件大?。?/td> | 513K |
| 代理商： | TLC2933IPWRG4 |
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TLC2933
HIGHPERFORMANCE PHASELOCKED LOOP
SLAS136B APRIL 1996 REVISED JANUARY 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = 2 mA
4.5
V
VOL
Low-level output voltage
IOL = 2 mA
0.5
V
VIT +
Positive input threshold voltage at TEST, VCO INHIBIT
1.5
2.5
3.5
V
II
Input current at TEST, VCO INHIBIT
VI = VDD or ground
±1
A
Zi(VCO IN)
Input impedance at VCO IN
VCO IN = 1/2 VDD
10
M
IDD(INH)
VCO supply current (inhibit)
See Note 4
0.01
1
A
IDD(VCO)
VCO supply current
See Note 5
14
35
mA
NOTES:
4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD, and PFD INHIBIT high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 k, VCO INHIBIT = ground, and PFD INHIBIT
high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = 2 mA
4.5
V
VOL
Low-level output voltage
IOL = 2 mA
0.2
V
IOZ
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or ground
±1
A
VIH
High-level input voltage at FINA, FINB
3.5
V
VIL
Low-level input voltage at FINA, FINB
1.5
V
VIT +
Positive input threshold voltage at PFD INHIBIT
1.5
2.5
3.5
V
Ci
Input capacitance at FINA, FINB
7
pF
Zi
Input impedance at FINA, FINB
10
M
IDD(Z)
High-impedance-state PFD supply current
See Note 6
0.01
1
A
IDD(PFD)
PFD supply current
See Note 10
2.6
8
mA
NOTES:
6. The current into LOGIC VDD when FINA and FINB = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
10. The current into LOGIC VDD when FINA and FINB = 50 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = ground, PFD OUT
open, and VCO OUT is inhibited.
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