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參數(shù)資料
| 型號(hào)： | TLC2933IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 30 MHz, PDSO14 |
| 封裝： | PLASTIC, SO-14 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 513K |
| 代理商： | TLC2933IPWRG4 |
TLC2933
HIGHPERFORMANCE PHASELOCKED LOOP
SLAS136B APRIL 1996 REVISED JANUARY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD (each supply, see Note 3)
VDD = 3 V
2.85
3
3.15
V
Supply voltage, VDD (each supply, see Note 3)
VDD = 5 V
4.75
5
5.25
V
Input voltage, VI (inputs except VCO IN)
0
VDD
V
Output current, IO (each output)
0
±2
mA
VCO control voltage at VCO IN
1
VDD
V
Lock frequency
VDD = 3 V
37
55
MHz
Lock frequency
VDD = 5 V
43
100
MHz
Bias resistor, RBIAS
VDD = 3 V
1.8
2.7
k
Bias resistor, RBIAS
VDD = 5 V
2.2
3
k
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and
separated from each other.
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = 2 mA
2.4
V
VOL
Low-level output voltage
IOL = 2 mA
0.3
V
VIT +
Positive input threshold voltage at TEST, VCO INHIBIT
0.9
1.5
2.1
V
II
Input current at TEST, VCO INHIBIT
VI = VDD or ground
±1
A
Zi(VCO IN)
Input impedance at VCO IN
VCO IN = 1/2 VDD
10
M
IDD(INH)
VCO supply current (inhibit)
See Note 4
0.01
1
A
IDD(VCO)
VCO supply current
See Note 5
5.1
15
mA
NOTES:
4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 k, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = 2 mA
2.7
V
VOL
Low-level output voltage
IOL = 2 mA
0.2
V
IOZ
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or ground
±1
A
VIH
High-level input voltage at FINA, FINB
2.1
V
VIL
Low-level input voltage at FINA, FINB
0.9
V
VIT +
Positive input threshold voltage at PFD INHIBIT
0.9
1.5
2.1
V
Ci
Input capacitance at FINA, FINB
5
pF
Zi
Input impedance at FINA, FINB
10
M
IDD(Z)
High-impedance-state PFD supply current
See Note 6
0.01
1
A
IDD(PFD)
PFD supply current
See Note 7
0.7
4
mA
NOTES:
6. The current into LOGIC VDD when FINA and FINB = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FINA and FINB = 30 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT
open, and VCO OUT is inhibited.
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