參數(shù)資料
型號(hào)： TLC2932IPW
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, 40 MHz, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 7/28頁(yè)
文件大小： 665K
代理商： TLC2932IPW
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired VCO output frequency
according to the system application requirements.
The Kp and KV values are obtained from the
operating characteristics of the device as shown
in Figure 24. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 24(b). KV is defined from
Figures 8, 9, 10, and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : count down divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. However,
for optimum temperature performance, a resistor value of 3.3 k
with a 3-V supply and a resistor value of 2.5
k
for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22
F capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
Dw
H ]
0.8 Kp
K
V
K
f
(
R)
Where
Kf (∞) = the filter transfer function value at ω = ∞
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2932
f REF
VOH
fMAX
fMIN
VIN MIN
VIN MAX
–2
π
2
π
–
π
0
π
Range of
Comparison
VOH
VOL
Kp =
VOH – VOL
4
π
KV =
2
π(fMAX – fMIN)
VIN MAX – VIN MIN
Figure 24. Example of a PLL Block Diagram
(a)
(c)
(b)
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TLC2932IPWR 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2932IPWRG4 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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