參數(shù)資料
型號(hào)： TLC2932IPW
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, 40 MHz, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 665K
代理商： TLC2932IPW
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
Supply voltage VDD (each supply see Note 3)
VDD = 3 V
2.85
3
3.15
V
Supply voltage, VDD (each supply, see Note 3)
VDD = 5 V
4.75
5
5.25
V
Input voltage, VI (inputs except VCO IN)
0
VDD
V
Output current, IO (each output)
0
±2
mA
VCO control voltage at VCO IN
0.9
VDD
V
Lock frequency (
×1 output)
VDD = 3 V
14
21
MHz
Lock frequency (
×1 output)
VDD = 5 V
22
50
MHz
Lock frequency (
×1/2 output)
VDD = 3 V
7
10.5
MHz
Lock frequency (
×1/2 output)
VDD = 5 V
11
25
MHz
Bias resistor RBIAS
VDD = 3 V
2.2
3.3
4.3
k
Bias resistor, RBIAS
VDD = 5 V
1.5
2.2
3.3
k
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = – 2 mA
2.4
V
VOL
Low-level output voltage
IOL = 2 mA
0.3
V
VIT
Input threshold voltage at SELECT, VCO INHIBIT
0.9
1.5
2.1
V
II
Input current at SELECT, VCO INHIBIT
VI = VDD or GND
±1
A
Zi(VCO IN)
Input impedance
VCO IN = 1/2 VDD
10
M
IDD(INH)
VCO supply current (inhibit)
See Note 4
0.01
1
A
IDD(VCO)
VCO supply current
See Note 5
5
15
mA
NOTES:
4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 k, VCO INHIBIT = GND, and PFD is inhibited.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = – 2 mA
2.7
V
VOL
Low-level output voltage
IOL = 2 mA
0.2
V
IOZ
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or GND
±1
A
VIH
High-level input voltage at FIN–A, FIN–B
2.7
V
VIL
Low-level input voltage at FIN–A, FIN–B
0.5
V
VIT
Input threshold voltage at PFD INHIBIT
0.9
1.5
2.1
V
Ci
Input capacitance at FIN–A, FIN–B
5
pF
Zi
Input impedance at FIN–A, FIN–B
10
M
IDD(Z)
High-impedance-state PFD supply current
See Note 6
0.01
1
A
IDD(PFD)
PFD supply current
See Note 7
0.1
1.5
mA
NOTES:
6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
inhibited.
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參數(shù)描述
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TLC2932IPWR 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2932IPWRG4 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933AIPW 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933AIPWG4 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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