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參數(shù)資料
| 型號： | TLC27X |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | FAMILY OF 500-UA/CH 3-MHZ RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS |
| 中文描述： | 3系列的500-UA/CH MHz的軌到軌輸出運算放大器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 514K |
| 代理商： | TLC27X |
μ
SGLS275 OCTOBER 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim
Parts
Release 9.1, the model generation
software used with Microsim
PSpice
. The Boyle macromodel (see Note 2) and subcircuit in Figure 30 are
generated using TLV27x typical electrical and operating characteristics at T
A
= 25
°
C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,”
IEEE Journal
of Solid-State Circuits,
SC-9, 353 (1974).
3
*DEVICE=amp_tlv27x_highVdd,OP AMP,NJF,INT
* amp_tlv_27x_highVdd operational amplifier ”macromodel”
* subcircuit updated using Model Editor release 9.1 on 05/15/00
* at 14:40 Model Editor is an OrCAD product.
*
* connections:
*
*
*
*
*
.subckt amp_tlv27x_highVdd 1 2 3 4 5
*
c1
11
12 457.48E15
c2
6
7
css
10
99 1.1431E12
dc
5
53 dy
de
54
5
dlp
90
91 dx
dln
92
90 dx
dp
4
3
egnd
99
0
fb
7
99 poly(5) vb vc ve vlp vln 0
non-inverting input
| inverting input
| | positive power supply
| | | negative power supply
| | | | output
5.0000E12
dy
dx
poly(2) (3,0) (4,0) 0 .5 .5
176.02E6 1E3 1E3 180E6
180E6
Figure 30. Boyle Macromodel and Subcircuit
PSpice
and
Parts
are trademarks of MicroSim Corporation.
ga
gcm
iss
hlim
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
6
0
10
90
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
0
6
4
0
2
1
9
11
12
5
99
4
99
0
53
4
8
0
92
D(Is=800.00E18)
D(Is=800.00E18 Rs=1m Cjo=10p)
NJF(Is=500.00E15 Beta=198.03E6 Vto=1)
NJF(Is=500.00E15 Beta=198.03E6 Vto=1)
11 12 16.272E6
10 99 6.8698E9
dc 1.3371E6
vlim 1K
10 jx1
10 jx2
100.00E3
61.456E3
61.456E3
10
10
150.51E3
149.58E6
dc 0
dc .78905
dc .78905
dc 0
dc 14.200
dc 14.200
IN
G
D
S
D
S
G
rp
IN+
rd1
rd2
rss
egnd
fb
ro2
ro1
vlim
OUT
ga
ioff
gcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve
de
dlp
dln
vln
hlim
vlp
10
4
1
11
12
53
54
9
6
8
5
7
+
91
90
92
vc
99
+
+
+
+
+
+
+
r2
2
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