
2004 Feb 20
8
Philips Semiconductors
Product specification
High speed CAN transceiver
TJA1041A
Pins RXD and ERR will reflect any wake-up requests
(provided that V
I/O
and V
CC
are present).
G
O
-
TO
-
SLEEP COMMAND MODE
The go-to-sleep command mode is the controlled route for
entering sleep mode. In go-to-sleep command mode the
transceiver behaves as if in standby mode, plus a
go-to-sleep command is issued to the transceiver. After
remaining in go-to-sleep command mode for the minimum
hold time (t
h(min)
), the transceiver will enter sleep mode.
The transceiver will not enter the sleep mode if the state of
pins STB or EN is changed or the UV
BAT
, pwon or
wake-up flag is set before t
h(min)
has expired.
S
LEEP MODE
The sleep mode is the second-level power saving mode of
the transceiver. Sleep mode is entered via the go-to-sleep
command mode, and also when the undervoltage
detection time on either V
CC
or V
I/O
elapses before that
voltage level has recovered. In sleep mode the transceiver
still behaves as described for standby mode, but now
pin INH is set floating. Voltage regulators controlled by
pin INH will be switched off, and the current into pin V
BAT
is reduced to a minimum. Waking up a node from sleep
mode is possible via the wake-up flag and (as long as the
UV
NOM
flag is not set) via pin STB.
Internal flags
The TJA1041A makes use of seven internal flags for its
fail-safe fallback mode control and system diagnosis
support. Table 1 shows the relation between flags and
operating modes of the transceiver. Five of the internal
flags can be made available to the controller via pin ERR.
Table 2 shows the details on how to access these flags.
The following sections describe the seven internal flags.
Table 2
Accessing internal flags via pin ERR
Notes
1.
Pin ERR is an active-LOW output, so a LOW level indicates a set flag and a HIGH level indicates a cleared flag. Allow
pin ERR to stabilize for at least 8
μ
s after changing operating modes.
Allow for a TXD dominant time of at least 4
μ
s per dominant-recessive cycle.
2.
Internal flag
Flag is available on pin ERR
(1)
Flag is cleared
UV
NOM
UV
BAT
pwon
no
no
in pwon/listen-only mode (coming from standby
mode, go-to-sleep command mode, or sleep mode)
in standby mode, go-to-sleep command mode, and
sleep mode (provided that V
I/O
and V
CC
are present)
in normal mode (before the fourth dominant to
recessive edge on pin TXD; note 2)
in normal mode (after the fourth dominant to
recessive edge on pin TXD; note 2)
in pwon/listen-only mode (coming from normal
mode)
by setting the pwon or wake-up flag
when V
BAT
has recovered
on entering normal mode
wake-up
on entering normal mode, or by setting the
pwon or UV
NOM
flag
on leaving normal mode, or by setting the
pwon flag
on re-entering normal mode
wake-up source
bus failure
local failure
on entering normal mode or when RXD is
dominant while TXD is recessive (provided
that all local failures are resolved)