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參數(shù)資料
| 型號(hào)： | TICPAL22V10Z-30INT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:18; No. Strands x Strand Size:19 x 30; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1180; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/5 Type EE RoHS Compliant: Yes |
| 中文描述： | EPICE CMOS可編程陣列邏輯電路 |
| 文件頁(yè)數(shù)： | 6/22頁(yè) |
| 文件大小： | 202K |
| 代理商： | TICPAL22V10Z-30INT |
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TICPAL22V10Z-25C, TICPAL22V10Z-30I
EPIC
CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
output logic macrocell (OLM) description
A great amount of architectural flexibility is provided by the user-configurable macrocell output options. The
macrocell consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like a standard
TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input. The Q and Q outputs
are made available to the output select multiplexer. The asynchronous reset and synchronous set controls are
available in all flip-flops.
The select multiplexers are controlled by programmable cells. The combination of these programmable cells
will determine which macrocell functions are implemented. It is this user control of the architectural structure
that provides the generic flexibility of this device.
output logic macrocell diagram
C1
G
0
3
Output Logic Macrocell
0
1
1
0
3
2
MUX
1S
1D
R
MUX
G1
1
1
SS
AR
From Clock Buffer
S1
S0
AR = asynchronous reset
SS = synchronous set
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