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參數(shù)資料
| 型號： | TIBPAL20R4-10CJT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CAP TANT LOESR 4.7UF 20V 10% SMD |
| 中文描述： | 高性能影響X PAL制式電路 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 292K |
| 代理商： | TIBPAL20R4-10CJT |
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE
IMPACT-X
PAL
CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
12
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
CC
be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu
tpd
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
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