參數(shù)資料
型號(hào): THAT120
廠商: Electronic Theatre Controls, Inc.
英文描述: Quad Low-Noise PNP Transistor Array
中文描述: 四低噪聲PNP晶體管陣列
文件頁(yè)數(shù): 1/2頁(yè)
文件大小: 43K
代理商: THAT120
THAT Corporation; 45 Sumner St., Milford, Massachusetts; 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
T H AT
Corporation
1
2
3
4
5
6
7
SUB
NC
8
9
10
11
12
13
14
Q2 Q1
Q4 Q3
Figure 1. Pin
Configuration
0.750±0.004
(19.05±0.10)
0.25±.004
(6.35±0.10)
0.32 Max.
(8.13)
0.060
(1.52)
Typ.
0.075
(1.91)
0.10 Typ.
(2.54)
0.018
(0.46)
0.125±0.004
(3.18±0.10)
1
0.010
(0.25)
Figure 2. Dual-In-Line Package Outline
Quad Low-Noise
PNP Transistor Array
THAT
120
FEATURES
Four Matched PNP Transistors
Low noise — 0.75
nV
Hz
High Speed — 325 MHz f
t
Excellent Matching - 500 V (typ)
Dielectrically Isolated
-25 V V
CEO
APPLICATIONS
Microphone Preamplifiers
Tape Head Preamplifiers
Current Sources
Current Mirrors
Log/Antilog Amplifiers
Multipliers
DESCRIPTION
THAT120 is a quad, large-geometry monolithic
PNP transistor array which combines low noise, high
speed and excellent parametric matching. The large
geometry typically results in 25
base spreading re-
sistance, producing 0.75
nV
Hz
voltage noise. This
makes these parts an excellent choice for low-noise
amplifier input stages.
Fabricated on a Complementary Bipolar Dielec-
trically Isolated process, all four transistors are elec-
trically isolated from each other by a layer of oxide.
The resulting low collector-to-substrate capacitance
produces a typical f
t
of 325 MHz, for AC perfor-
mance similar to 2N3906-class devices. The dielec-
tric isolation also minimizes crosstalk and provides
complete DC isolation.
Substrate biasing is not required for normal oper-
ation, though the substrate should be grounded to
optimize speed. The one-chip construction assures
excellent parameter matching and tracking over tem-
perature.
0.050
(1.27)
Typ
0.245
(6.2)
Max
0.157
(3.99)
Max
0.018 (0.46)
Max
0.344 (8.74)
Max
0.069
(1.75)
Max
0.010
(0.25)
Max
1
Figure 3. Surface Mount Package Outline
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