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參數資料
| 型號： | TH58NVG1S3AFT |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝馬鞍山數字集成電路硅柵CMOS |
| 文件頁數： | 16/32頁 |
| 文件大?。?/td> | 368K |
| 代理商： | TH58NVG1S3AFT |
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2003-05-19A
16/32
TH58NVG1S3AFT05
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
1 page = 2112bytes
1 block = 2112 bytes x 64 pages = (128K + 4K) bytes
Capacity = 2112bytes x 64pages x 2048blocks
An address is read in via the I/0 port over four
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
First cycle
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Second cycle
L
L
L
L
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
CA0 to CA11 : Column address
PA0 to PA16 : Page address
PA6 to PA16 : Block address
PA0 to PA5 : NAND address in block
Fourth cycle
PA15
PA14 PA13 PA12
PA11
PA10
PA9
PA8
Fifth cycle
L
L
L
L
L
L
L
PA16
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE,
CE
,
WE
,
RE
and
WP
signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
WE
RE
WP
*
1
Command Input
H
L
L
H
*
Data Input
L
L
L
H
H
Address input
L
H
L
H
*
Serial Data Output
L
L
L
H
*
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
During Reading (Busy)
*
*
*
*
*
*
Program, Erase Inhibit
*
*
*
*
*
L
Standby
*
*
H
*
*
0 V/Vcc
H: V
IH
, L: V
IL
,
*
: V
IH
or V
IL
*
1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
Figure 2. Schematic Cell Layout
64Pages
= 1block
8I/O
2112
I/O1
I/O8
64
2048
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