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參數(shù)資料
| 型號： | TH50VSF3582AASB |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝多芯片集成電路硅柵CMOS |
| 文件頁數(shù)： | 18/50頁 |
| 文件大小： | 548K |
| 代理商： | TH50VSF3582AASB |
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TH50VSF3582/3583AASB
2001-06-08 18/50
COMMAND WRITE/PROGRAM/ERASE CYCLE
LOAD CAPACITANCE
30pF
100pF
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
t
CMD
Command Write Cycle Time
70
80
ns
t
AS
Address Set-up Time
/
BYTE Set-up Time
0
0
ns
t
AH
Address Hold Time
/
BYTE Hold Time
40
40
ns
t
AHW
Address Hold Time from
WE
High level
20
20
ns
t
DS
Data Set-up Time
40
40
ns
t
DH
Data Hold Time
0
0
ns
t
WELH
WE Low-Level Hold Time
( WE Control)
40
40
ns
t
WEHH
WE High-Level Hold Time
( WE Control)
20
20
ns
t
CES
CEF
Set-up Time to WE Active
( WE Control)
0
0
ns
t
CEH
CEF
Hold Time from WE High Level ( WE Control)
0
0
ns
t
CELH
CEF
Low-Level Hold Time
(
CEF
Control)
40
40
ns
t
CEHH
CEF
High-Level Hold Time
(
CEF
Control)
20
20
ns
t
WES
WE Set-up time to
CEF
Active
(
CEF
Control)
0
0
ns
t
WEH
WE Hold Time from
CEF
High Level (
CEF
Control)
0
0
ns
t
OES
OE
Set-up Time
0
0
ns
t
OEHP
OE
Hold Time (Toggle, Data Polling)
90
90
ns
t
OEHT
OE
High-Level Hold Time (Toggle)
20
20
ns
t
BEH
Erase Hold Time
50
50
μ
s
t
VCS
V
CCf
Set-up Time
500
500
μ
s
t
BUSY
Program/Erase Valid to
BY
/
RY
Delay
90
90
ns
t
RP
RESET
Low-Level Hold Time
500
500
ns
t
READY
RESET
Low-Level to Read Mode
20
20
μ
s
t
RB
BY
/
RY
Recovery Time
0
0
ns
t
RH
RESET
Recovery Time
50
50
ns
t
CEBTS
CEF
Set-up time BYTE Transition
5
5
ns
t
SUSP
Program Suspend Command to Suspend Mode
1.5
1.5
μ
s
t
RESP
Program Resume Command to Program Mode
1
1
μ
s
t
SUSE
Erase Suspend Command to Suspend Mode
15
15
μ
s
t
RESE
Erase Resume Command to Erase Mode
1
1
μ
s
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