參數(shù)資料
型號(hào)： TE28F128P30xxx
廠商： Intel Corp.
英文描述： Intel StrataFlash Embedded Memory
中文描述： 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁(yè)數(shù)： 58/102頁(yè)
文件大?。?/td> 1609K
代理商： TE28F128P30XXX
1-Gbit P30 Family
April 2005
58
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on DQ[15:0] for one or two clock cycles. This period of time is called the “
data cycle
”. When DH
is set, output data is held for two clocks (default). When DH is cleared, output data is held for one
clock (see
Figure 30
). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or two clocks. A
method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
t
CHQV
(ns) + t
DATA
(ns)
≤
One CLK Period (ns)
t
DATA
= Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
t
CHQV
= 20 ns and t
DATA
= 4 ns. Applying these values to the formula above:
20 ns + 4 ns
≤
25 ns
The equation is satisfied and data will be available at every clock period with data hold setting at
one clock. If t
CHQV
(ns) + t
DATA
(ns) >
One CLK Period (ns), data hold setting of 2 clock periods
must be used.
Table 24.
WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
High-Z
1
CE# =’0’, OE# = ‘0’
Active
1
Synchronous Array Reads
Active
1
Synchronous Non-Array Reads
Active
1
All Asynchronous Reads
Deasserted
1
All Writes
High-Z
1,2
Notes:
1.
2.
Active:
WAIT is asserted until data becomes valid, then deasserts
When OE# = V
IH
during writes, WAIT = High-Z
Figure 30.
Data Hold Timing
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
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