2004 Jul 05
9
Philips Semiconductors
Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
TDA9965A
Note
1.
Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
I
i(ADCIN)
V
RB
ADC input current
ADC reference voltage
bottom
ADC reference voltage top
differential non-linearity
sampling delay
2
1.30
+120
μ
A
V
V
RT
DNL
t
d(s)
Total chain characteristics (CTH + PGA + ADC)
3.65
±
0.5
±
0.9
5
V
LSB
ns
ramp input; f
pix
= 30 MHz
see Fig.5
t
d(SHD-CLKADC)
delay between
SHD and CLKADC
V
i(IN)
= 1000 mV;
transition (95%) in 1 pixel;
code f
co(CTH)
= 0000;
code G
PGA
= 128; see Fig.5
V
i(IN)
= 32 mV;
transition (95%) in 1 pixel;
code f
co(CTH)
= 0000;
code G
PGA
= 128; see Fig.5
G
PGA
= 0 dB;
code f
co(CTH)
= 0000
G
PGA
= 30 dB;
code f
co(CTH)
= 0000; note 1
see Fig.11
15
ns
t
h(SHD-CLKADC)
SHD hold time compared
to CLKADC
0
ns
N
tot(rms)
total noise from CTH input
to ADC output
(RMS value)
0.85
LSB
6
LSB
O
CCD(max)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
equivalent input noise
(RMS value)
200
+200
mV
V
n(i)(eq)(rms)
G
PGA
= 30 dB;
code f
co(CTH)
= 0000; note 1
90
μ
V
Digital outputs (f
pix
= 40 MHz; C
L
= 10 pF)
V
OH
V
OL
t
h(o)
t
d(o)
HIGH-level output voltage
LOW-level output voltage
output hold time
output delay
I
OH
=
1 mA
I
OL
= 1 mA
see Fig.5
V
CCO
= 5.25 V
V
CCO
= 3 V
V
CCO
0.5
0
10
V
CCO
0.5
25
31
V
V
ns
ns
ns
20
26
Serial interface
f
SCLK(max)
maximum clock frequency
of serial interface
5
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
