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參數(shù)資料
| 型號： | TDA9840T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | DIODE 1SMC28AT3 TRANSZORB 1500W SMT |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOP-20 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 200K |
| 代理商： | TDA9840T |
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1998 Jul 03
15
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Level adjustment register
The information about the level adjustment of the AF
channel V
i 2
(pin 8) is stored in the level adjustment
register (see Table 10). There are 10 steps (positions) of
the AF level adjustment stage. The level range is from
2.5 dB up to
2.0 dB in 0.5 dB steps.
After a power-on reset, the data byte of the level
adjustment register will be set to (00)
HEX
: 0 dB gain at the
AF input V
i 2
.
Stereo adjustment register
The information about the stereo adjustment of the
AF channel V
i 1
(pin 7) is stored in the stereo adjustment
register (see Table 11). There are 50 steps (positions) of
the AF stereo adjustment stage. The stereo range is from
2.5 dB up to
2.4 dB in 0.1 dB steps.
After a power-on reset, the data byte of the stereo
adjustment register will be set to (00)
HEX
: 0 dB gain at the
AF input V
i 1
.
Test register (also used for fast mode)
Table 12 shows the meaning of the test register. The
integration time of the integrator is approximately 1 s
(normal mode, default). If the data byte of this register is
set to HIGH, the integration time is reduced from
approximately 1 to approximately 0.5 s (fast mode, test
mode). The pull-in ranges of the identification PLLs are
changed to:
Stereo:
0.89/+1.15 Hz
Dual:
±
2.05 Hz.
If the integration time of the integrator is switched from one
mode to the other (i.e. from fast mode/test mode to normal
mode), the status register bits D5 and D6 might set to zero
internally (MONO). Therefore, the previous status register
information has to be stored by the microcontroller until the
transmitter status is detected again by the identification
circuit (now in the new mode) the first time.
The data byte of the test register can be reset in two
different ways to (00)
HEX
: integration time approximately
1 s, normal mode:
after a power-on reset, for instance by switching the
power supply V
p
off and on again
data transmission via I
2
C-bus for the test register
(see Table 12).
Level and stereo adjustment
For the level and stereo adjustment of both AF channels
V
i 1
and V
i 2
, the following procedure will be recommended.
Level adjustment of the AF channel V
Feeds AF signal at the input V
i 2
Sets the data byte of the switch register (dual mode)
to (1A)
HEX
Measures the signal at the outputs V
o 2
or V
o 4
Adjusts the output level with the level adjustment
register.
Stereo adjustment of the AF channel V
i 1
Feeds AF stereo signals at the inputs V
i 1
((L+R)/2) and
V
i 2
(R)
Sets the data byte of the switch register (stereo mode)
to (2A)
HEX
Measures the crosstalk attenuation between V
o 1
and
V
o 2
or V
o 3
and V
o 4
Adjusts the crosstalk attenuation with the stereo
adjustment register.
During the stereo adjustment the data byte of the level
adjustment register does not change.
After the level and stereo adjustment, the bytes of the level
and stereo adjustment register must be stored by the
microcontroller in a memory. (To avoid mis-adjustment it
would be wise to compare the stored bytes with the proper
adjustment bytes). If the PONRES bit of the status register
will be set to HIGH (see status register) the data bytes for
these both registers must be sent out of the memory to the
TDA9840 via I
2
C-bus. Also the data byte of the switch
register (see Table 7) must be changed, because the
AF outputs are muted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9840 | TV and VTR stereo/dual sound processor with digital identification(帶數(shù)字識別和IIC總線控制的TV和VTR立體/雙聲道處理器) |
| TDA9845T | TV and VTR stereo/dual sound processor with digital identification |
| TDA9845 | TV and VTR stereo/dual sound processor with digital identification and I 2 C-bus control(帶數(shù)字識別的TV和VTR立體/雙聲道處理器) |
| TDA9847 | TV and VTR stereo/dual sound processor with digital identification |
| TDA9847T | TV and VTR stereo/dual sound processor with digital identification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9845 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9845T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9847 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9847T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9850 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder |
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