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參數(shù)資料
| 型號： | TDA9840T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | DIODE 1SMC28AT3 TRANSZORB 1500W SMT |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOP-20 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 200K |
| 代理商： | TDA9840T |
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1998 Jul 03
14
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
I
2
C-BUS PROTOCOL FOR THE TV AND VTR
STEREO/DUAL SOUND PROCESSOR TDA9840
The TDA9840 has an I
2
C-bus interface with five registers:
status, test, switch, level and stereo adjustment register
controlled by a microcontroller via I
2
C-bus. The status
register can be read and the other registers are write
registers. The status byte represents the transmitter status
detected by the identification circuit and the power-on
reset status. The switch register controls the source
selectors of the AF signal part, and the level and stereo
adjustment register set the input level and stereo
adjustment stage. Additionally, a test register is built-in to
reduce the detection time of the identification circuit (test
mode, fast mode respectively).
I
2
C-bus transceiver and data-handling
(bus specification)
The TDA9840 is controlled by a microcomputer via the
bidirectional 2-line I
2
C-bus. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
When the bus is free, both lines are HIGH. The data on the
SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only
change, when the clock signal on the SCL line is LOW.
The set-up and hold times are specified in the
Chapter “Characteristics”.
A HIGH-to-LOW transition of the SDA line, while SCL is
HIGH, is defined as the start condition. A LOW-to-HIGH
transition of the SDA line, while SCL is HIGH, is defined as
the stop condition. The bus transceiver will be reset on the
reception of a start condition. The bus is considered to be
busy after the start condition. The bus is considered to be
free again after a stop condition.
Data format transmitter mode
For the data transmission no subaddress is to be
transmitted, because there is only one read register
implemented. So the total number of bytes reduces from
three to two. The second byte represents the status of
the IC.
Status register
(see Table 4)
The bit D7 (PONRES) represents the status of the IC and
indicates whether the power-on reset was activated by
switching-on the supply voltage or a supply voltage
breakdown. If so, the I
2
C-bus transceiver, the digital PLLs
and integrators are initialized and the PONRES bit is set to
HIGH. After a successful reading of the status register, the
bit D7 will be reset to LOW.
The bits D5 and D6 represent the transmitter status
detected by the identification circuit (stereo, dual or mono
transmission). The other bits are set to 0 (default).
Data format for the receiver
Table 1
Registers for receiver mode (see Table 6)
The port register is without function, because this IC has
no control ports as TDA8415/6/7. A data byte for the
subaddress (01)
HEX
will not be stored in any register. An
acknowledge will be sent to the microcontroller.
The first byte of the data transmission is the slave address
and the second byte is the subaddress indicating the data
register in which the data shall be stored. Starting from
subaddress (00)
HEX
the n-th data byte will automatically be
stored under subaddress n
1.
All 8 bits of the subaddress are decoded by the device.
The subaddresses from (04)
HEX
to (FF)
HEX
are forbidden
for the user. If the I
2
C-bus transceiver receives
subaddresses from (05)
HEX
to (FF)
HEX
, no acknowledge
will be sent back to the microcontroller.
Switch register
The source selector is controlled by the switch register.
Table 7 shows the modes of operation. Note, that in the
event of the external operation mode, no further selection
is possible.
REGISTER
VALUE
Switch register
Port register
Level adjustment register
Stereo adjustment register
Test register
(00)
HEX
(01)
HEX
(without function)
(02)
HEX
(03)
HEX
(04)
HEX
相關PDF資料 |
PDF描述 |
|---|---|
| TDA9840 | TV and VTR stereo/dual sound processor with digital identification(帶數(shù)字識別和IIC總線控制的TV和VTR立體/雙聲道處理器) |
| TDA9845T | TV and VTR stereo/dual sound processor with digital identification |
| TDA9845 | TV and VTR stereo/dual sound processor with digital identification and I 2 C-bus control(帶數(shù)字識別的TV和VTR立體/雙聲道處理器) |
| TDA9847 | TV and VTR stereo/dual sound processor with digital identification |
| TDA9847T | TV and VTR stereo/dual sound processor with digital identification |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9845 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9845T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9847 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9847T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV and VTR stereo/dual sound processor with digital identification |
| TDA9850 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder |
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