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參數(shù)資料
| 型號： | TDA8779H-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 102K |
| 代理商： | TDA8779H-T |
1999 Sep 16
10
Philips Semiconductors
Product specication
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779H
Notes
1. The noise floor is the maximum value of the output spectrum without taking into account fundamental and harmonics
of the input signal up to the 6th harmonic.
2. Harmonics are obtained via a Fast Fourier Transformer (FFT) treatment taking 8k acquisition points per period.
3. It is recommended that the DAC output voltage is AC coupled in order to achieve optimum performance.
TRANSFER FUNCTION
INLD
integral non linearity
ramp input;
fCLK =20MHz
±0.4
±1.25
LSB
DNLD
differential non linearity
ramp input;
fCLK =20MHz
±0.35
±1.5
LSB
tst
settling time
10% to 90% full-scale;
Tamb =25 °C
8.0
ns
10% to 90% for 10%
full-scale; Tamb =25 °C
7
ns
MATCHING BETWEEN CHANNEL I AND Q
V
amplitude matching
fo = 4.43 MHz;
fCLK = 20 MHz;
Tamb =25 °C
0.2
6
%
phase matching
fo = 4.43 MHz;
fCLK = 20 MHz;
Tamb =25 °C
2
deg
DYNAMIC RANGE; note 1
NF
noise oor
fo = 4.43 MHz;
fCLK =20MHz
56
61
dB
SPURIOUS FREE DYNAMIC RANGE
SFDR
spurious free dynamic
range
fo = 4.43 MHz;
fCLK =20MHz
55
dB
STANDBY MODE OUTPUT DELAY; STDBYD; Tamb =25 °C
td(stb)LH
standby delay
(LOW-to-HIGH transition)
100
s
td(stb)HL
start-up delay
(HIGH-to-LOW transition)
100
s
CROSSTALK ON THE DAC
α
ct
crosstalk on the DAC
fCLK(DAC) = 16.384 MHz;
fCLK(ADC) = 8.192 MHz;
Tamb =25 °C; one DAC
switching between input
codes 0 and 1023 the
other DAC set at the
middle code; both ADCs
1 V (p-p) sine wave at
4 MHz; incoherent
60
75
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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