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參數(shù)資料
| 型號： | TDA8779H-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 102K |
| 代理商： | TDA8779H-T |
1999 Sep 16
8
Philips Semiconductors
Product specication
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779H
tCL
clock pulse width LOW
20
ns
tr
clock rise time
4
ns
tf
clock fall time
4
ns
ANALOG SIGNAL PROCESSING
Linearity
INLA
integral non linearity
ramp input;
fCLK =20MHz
±2.25
±4
LSB
DNLA
differential non linearity
maximum missing codes
guaranteed: 20
full-scale; ramp input;
fCLK =20MHz
+1.55 to
0.9 +2.8 to 1.1 LSB
Noise oor; note 1
NF
noise oor
fi = 4.43 MHz; 20 Msps
55
71
dB
Harmonics; note 2
THD
total harmonic distortion
fi = 4.43 MHz; 20 Msps
50
58
dB
Spurious free dynamic range
SFDR
spurious free dynamic
range
fi = 4.43 MHz; 20 Msps
50
58
dB
Matching between the I and Q channels
V
amplitude matching
fi = 4.43 MHz;
fCLK = 20 MHz;
Tamb =25 °C
0.1
6
%
phase matching
fi = 4.43 MHz;
fCLK = 20 MHz;
Tamb =25 °C
0.05
2
deg
Bandwidth
B
bandwidth (maximum
attenuation of
0.3 dB)
full-scale sine wave;
Tamb =25 °C
30
MHz
50% full-scale sine wave;
Tamb =25 °C
30
MHz
TIMING (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL = 15 pF; Tamb =25 °C (see Fig.3)
tds
sampling delay time
11
ns
th
output hold time
5
ns
td
output delay time
VCCO = 3.3 V
12
ns
VCCO = 2.7 V
13
ns
3-STATE OUTPUT DELAY TIMES;Tamb =25 °C (see Fig.4)
tdZH
output delay enable HIGH
10
ns
tdZL
output delay enable LOW
7.7
ns
tdHZ
output delay disable HIGH
15.5
ns
tdLZ
output delay disable LOW
14.9
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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