參數(shù)資料
型號(hào): TDA8757HL
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: Triple 8-bit ADC 170 Msps
中文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: HEAT SINK, PLASTIC, LQFP-144
文件頁數(shù): 21/37頁
文件大小: 895K
代理商: TDA8757HL
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Preliminary data
Rev. 07 — 28 February 2002
21 of 37
9397 750 09457
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The default programmed value is as follows:
No external clock: bit ‘Ckext’ is logic 0
Phase shift for CKDATA is 0 degrees.
9.1.8
DEMUX register
The default programming is:
Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1
CKREFO with positive polarity: bit ‘Ckrp’ = 0
CKDATA not reversed: bit ‘Ckdp’ = 0
CKDATA not delayed: bit ‘Ckdd’ = 0
De-multiplexed outputs: bit ‘Dmx’ = 1
Interleaved outputs: bit ‘Shift’ = 1
Odd pixels on port A: bit ‘Odda’ = 1.
9.1.9
Power-down mode
When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
When the device is in Power-down mode (pin PD = HIGH), the previously
programmed register values remain unaffected.
9.2 I
2
C-bus protocol
The address of the circuit for the I
2
C-bus is 1001 1XX0.
Bits ‘A1’ and ‘A0’ are fixed by the potential on pins A2 and A1. Bit ‘RW’ must always
be equal to logic 0 because it is not possible to read the data in the register. The
timing and protocol for the I
2
C-bus are standard. Two sequences are available;
see
Table 13
and
14
.
Table 11: Phase registers bits
P4
P3
0
0
0
0
...
...
1
1
1
1
P2
0
0
...
1
1
P1
0
0
...
1
1
P0
0
1
...
0
1
Phase shift (deg)
0
11.25
...
337.5
348.75
Table 12: Register format
A6
A5
1
0
A4
0
A3
1
A2
1
A1
A2
A0
A1
RW
0
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