參數(shù)資料
型號: TDA8757HL
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: Triple 8-bit ADC 170 Msps
中文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: HEAT SINK, PLASTIC, LQFP-144
文件頁數(shù): 20/37頁
文件大小: 895K
代理商: TDA8757HL
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Preliminary data
Rev. 07 — 28 February 2002
20 of 37
9397 750 09457
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Bits ‘Vco1’ and ‘Vco0’ control the VCO gain.
The default programmed value is as follows:
Internal resistance = 2.25 k
VCO gain = 70 MHz/V.
9.1.6
Divider register
This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The
default programmed value is 0110 1001 1000 = 1688.
The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed
before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for
the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be
noted that if the I
2
C-bus programming is done in mode 1 and the bit ‘Di0’ has to be
toggled, then the registers have to be loaded twice to update the divider ratio.
9.1.7
Phase register
Bit ‘Ckext’ is logic 0 when the PLL clock is used, and logic 1 when the external clock
is used.
Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see
Figure 3
).
Bits ‘P4’ to ‘P0’ are used to program the phase shift for the clock pixel.
Table 9:
Z2
0
0
0
0
1
1
1
1
VCO register bits
Z1
0
0
1
1
0
0
1
1
Z0
0
1
0
1
0
1
0
1
Resistance (k
)
high-impedance
9
6.4
4.5
3.2
2.25
1.6
1.1
Table 10: VCO gain control
Vco1
Vco0
VCO gain (MHz/V)
Pixel clock
frequency range
(MHz)
10 to 20
20 to 40
40 to 85
85 to 170
0
0
1
1
0
1
0
1
12
20
40
70
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