參數(shù)資料
型號(hào): TDA8757CHV/17
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-612-1, HLQFP-144
文件頁數(shù): 11/38頁
文件大小: 894K
代理商: TDA8757CHV/17
Philips Semiconductors
TDA8757C
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 14 August 2002
19 of 38
9397 750 10111
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The default programmed value is:
Programmed code = 127
Clamp code = 0
ADC output = 0.
9.1.3
Coarse and Fine registers
The coarse register enables the gain control and the AGC gain. The ne register
controls the reference voltage, control pins SW1 and SW2, and the power-down
mode.
The coarse register programming equation is as follows:
(3)
Where: Vref = 2.5 V.
The gain correspondence is given in Table 6. The gain is linear with reference to the
programming code (NFINE = 0).
The default programmed value is as follows:
NCOARSE =32
Gain = 0.825
Vi to be full-scale = 1.212.
To modulate this gain, the ne register is programmed using the above equation. With
a full-scale ADC input, the ne register resolution is a 1
2 LSB peak-to-peak
(see Table 7 for NCOARSE = 32).
The default programmed value is: NFINE =0.
In addition bit PWD (in register FINER) sets the device into power-down mode as well
as the data and clock outputs into high-impedance:
PWD = 0: chip active
PWD = 1: chip in power-down mode and data and clock outputs in high-impedance.
Table 6:
Typical gain correspondence (COARSE)
NCOARSE
Gain
Vi to be full-scale (V)
32
0.825
1.212
99
2.5
0.4
Table 7:
Typical gain correspondence (FINE)
NFINE
Gain
Vi to be full-scale (V)
0
0.825
1.212
31
0.878
1.139
GAIN
N
COARSE
1
+
V
ref
1
N
FINE
32
16
×
------------------
------------------------------------------------
1
16
------
×
N
COARSE
1
+
V
ref . 512
N
FINE
()
------------------------------------------------
32
×
==
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