參數(shù)資料
型號(hào)： TDA7529TR
廠商： 意法半導(dǎo)體
英文描述： RF front-end for AM/FM DSP car-radio with IF sampling
中文描述： RF前端的調(diào)幅/調(diào)頻DSP的汽車無(wú)線電IF采樣
文件頁(yè)數(shù)： 35/60頁(yè)
文件大?。?/td> 437K
代理商： TDA7529TR
TDA7529
Registers description
35/60
6
Registers description
Figure 16.
Registers description
No
name
r/w
MSB (7)
6
5
4
3
2
1
LSB (0)
Power
on
default
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0 Short reg
1 ADCctrl
2 GPIOval
3 AGCmixCtrl
4 Misc1
5 DivR
6 IFAGC_SH
7 FMAGC
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
ShAGC
ADCs1
GPIO6_MISO
FMAGCpwr
WAIT60ms(2)
divr5
IFAGCthr1
FMthr1
Vthr5
ShPLL
ADCs0
GPIO5_Aout
AMAGCpwr
WAIT60ms(1)
divr4
IFAGCthr0
FMthr0
Vthr4
ADCen
RCenable
CP_curr_switch
BalunoutIMP
disvcc
divr2
GPIOen
ADCautomode
GPIO2io
Mixout1
PLLtest
divr1
GPIO5 output
FMAGCmodeV1
Vthr1
IMRF1
IMRG1
divRen
DS2
PLLT1
VCOMag1
PWR
Temp_pwr
GPIO1io
Mixout2
AMAGC_Isink
divr0
IFsection_pwr
FMAGCmodeV0
Vthr0
IMRF0
IMRG0
PLLpwr
DS1
PLLT0
VCOMag0
ADCclk
ADCs2
GPO8_AMAGCv
IFin1_AM_FM
WAIT60ms(4)
divr7
IFAGC_FM_AM
FMthr3
AMAGCfat
IFAMP_Ictrl2
IMRph3
GPO7_FMAGCv
KeyAGCen
WAIT60ms(3)
divr6
IFAGCthr2
FMthr2
AFH_MUX
IFAMP_Ictrl1
IMRph2
DZ3
MODE2
PFD_D1
EnSMOOTH
GPO4_AMcas
MixinFMAM
WAIT60ms(0)
divr3
FMAGCmodeC1
Vthr3
FMAGCmodeC0
Vthr2
IMRF2
IMRG2
SWfref
DS3
PLLT2
8 FM_AM_Vthr
9 MIXalign1
10 MIXalign2
11 PLLctrl
12 PLLctrl2
13 PLLtest
14 Misc2
15 WAIT_LOCK
IredH
IMRph1
DZ2
MODE1
PFD_D0
reg48sel
IredL
IMRph0
DZ1
MODE0
PLLT4
IFAMP_Ictrl0
Casc_ctrl
IMRG3
CPcur_800u
DS4
PLLT3
DZ4
FUNC
POL
IFAGCin4ctrl
WAIT LOCK(4)
IFAGCtcAM
AMthr3
GPO8hl
IFin0_Std_IBOC
WAIT1ms(5)
divnA20
divnA12
divnA4
VCO1r
CPAh3
DAC1A8
DAC2A8
IQselA
WAIT2ms(5)
WAIT0.5ms(5)
RCfreq_1
WAIT LOCK(0)
FMtc3
AMAGCmodeC1
GPO4hl
MixinFM
WAIT1ms(1)
divnA16
divnA8
divnA0
divVA3
CPAl3
DAC1A3
DAC2A3
DAC2A0
WAIT2ms(1)
WAIT0.5ms(1)
RCfreq_0
DIVVtest
FMtc2
AMAGCmodeC0
WAIT LOCK(3)
IFAGCtcFM
AMthr2
GPO7hl
IFAmpgainA2
WAIT1ms(4)
divnA19
divnA11
divnA3
divVA6
CPAh2
DAC1A6
DAC2A6
VCOsw
WAIT2ms(4)
WAIT0.5ms(4)
WAIT LOCK(2)
AMtc1
AMthr1
GPIO6hl
IFAmpgainA1
WAIT1ms(3)
divnA18
divnA10
divnA2
divVA5
CPAh1
DAC1A5
DAC2A5
WAIT LOCK(1)
AMtc0
AMthr0
GPIO5hl
IFAmpgainA0
WAIT1ms(2)
divnA17
divnA9
divnA1
divVA4
CPAh0
DAC1A4
DAC2A4
VCOext
FMtc1
LOCK_bit
FMtc0
AMAGCmodeV0
GPIO1hl
16 AGCtc_A
17 AMAGC_A
18 GPIOm_A
19 IFCTRL_A
20
21 DivN_A1
22 DivN_A2
23 DivN_A3
24 DivV_A
25 CPcur_A
26 DAC1_A
27 DAC2_A
28 PLL_DAC_A
29 Misc4_A
30
31
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
AMAGCmodeV1
GPIO2hl
RCtest
AMAGCinbuffer
WAIT1ms(0)
divnA15
divnA7
divnA14
divnA6
divnA13
divnA5
divVA2
CPAl2
DAC1A2
DAC2A2
DAC1A0
WAIT2ms(0)
WAIT0.5ms(0)
divVA1
CPAl1
DAC1A1
DAC2A1
DAC2off
divVA0
CPAl0
DAC1A1
DAC2A1
DAC1off
MIN16
AGCtest0
WAIT2ms(3)
WAIT0.5ms(3)
WAIT2ms(2)
WAIT0.5ms(2)
AGCtest1
IF test
ADC test
this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output
all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output
ADCDAC5
ADCDAC4
ADCDAC3
ADCDAC2
ADCDAC1
ADCDAC0
32 AGCtc_B
33 AMAGC_B
34 GPIOm_B
35 IFCTRL_B
36 AMFilt_B
37 DivN_B1
38 DivN_B2
39 DivN_B3
40 DivV_B
41 CPcur_B
42 DAC1_B
43 DAC2_B
44 PLL_DAC_B
45 Misc4_B
46
47
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
48 READ_Status
49 READ_ADC
r
r
lock
GPIO6r
ADC5
GPIO5r
ADC4
MaskMetal1
ADC3
MaskMetal0
ADC2
MaskSet1
ADC1
MaskSet0
ADC0
00h
00h
ADCok
ADCstart
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