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參數(shù)資料
| 型號： | TDA7529TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | RF front-end for AM/FM DSP car-radio with IF sampling |
| 中文描述： | RF前端的調(diào)幅/調(diào)頻DSP的汽車無線電IF采樣 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大?。?/td> | 437K |
| 代理商： | TDA7529TR |
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TDA7529
Tuning state machine
33/60
Table 25.
5.5
Register SWAP
Some of these modes contain one or two register "swap" operation(s). The changes within
the register structure during a swap operation depend on the operating mode of the chip.
If the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1),
which is necessary to take advantage of the tuning state machine, it is suggested that the
microprocessor write data only in the normal register bank (bytes from 16 to 31), because
the state machine itself takes care of exchanging the content of the normal register bank
with that of the shadow bank (bytes from 32 to 47) during a swap. The normal registers are
intended to be written to by the radio microprocessor, whereas the registers that actually
control the device circuits are the shadow ones.
In any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is
actually used to drive the device circuits, should not be touched after setting them to 0 after
reset because they are automatically updated by the tuning state machine.
Values of the programmable wait times
PARAMETER NAME
REGISTER
VALUE
TIME
T
plllock
Byte 15 bits<7:3>
min.
00000
20 us
default
00110
1 ms
maximum
11111
5 ms
T
0.5ms
Byte 30 bits<7:2>
min.
000000
70 us
default
000101
0.5 ms
maximum
111111
5 ms
T
1ms
Byte 20 bits<7:2>
min.
000000
10 us
default
001100
1 ms
maximum
111111
5 ms
T
2ms
Byte 29 bits<7:2>
min.
000000
50 us
default
011000
2 ms
maximum
111111
5 ms
T
60ms
Byte 04 bits<7:3>
min.
00000
1 ms
default
10111
60 ms
maximum
11111
80 ms
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