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參數(shù)資料
| 型號(hào)： | TDA7522 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Digital Servo & Decoder(用于CD-ROM的數(shù)字伺服和解碼器) |
| 中文描述： | 數(shù)字伺服 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 183K |
| 代理商： | TDA7522 |
TDA7522
10/23
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
Shock Proof
WP1: Preset of Write Pointer Lower
WP2: Preset of Write Pointer Upper
CSR: Control/Status Register
WA1: Latest Stored valid Audio Frame Lower
WA2: Latest Stored valid Audio Frame Upper
RL1: Ram Level Lower
RL2: Ram Level Upper
DRR: Dummy Read to reset W/R Counter
00h
00h
00h
00h
00h
00h
00h
00h
R/W Register
R/W Register
R/W Register
Read only
Register
Read only
Register
Read only
Register
Read only
Register
Read only
Register
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
(HSY)
Bit Detection
and Clock
Recovery
PHIGAIN: Phase Gain
FRQCFG: Frequency Loop Configuration
FRQGAIN: Frequency Loop Gain
FRQ_L: Present Loop Output Freq Lower
FRQ_U: Present Loop Output Freq Upper
FRQI_L: Initial Loop Output Freq Lower
FRQI_U: Initial Loop Output Freq Upper
BD_INTEN: Interrupt Enable
BD_INTSRC: Interrupt Source Register
PHICFG: Configuration for Phase Loop
PLLGAIN: LP Filter Coefficients for ADPLL
PLL_SETUP: Overall control/configuration
PLL_STATUS: PLL mode Status Flag
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W Register
R/W Register
R/W Register
R Register
R Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R Register
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
Event
Detection
SETUP: Overall control/configuration
STATUS: Status Flag
RAMP: Peak detector decoding rate
DROPTHR: Dropout Threshold
DROPTIM: Dropout Timeout
FOCTHR: Focus Thres. Quality
MIRRPARS: Parameters for mirror signal
MIRRTHR: Thr for mirror env. for trk search
MIRRHYS: Hysteresis for MIRRTHR
TRK_CNTL: Tracking Counter Lower
TRK_CNTU:Tracking Counter Upper
ED_INTEN: Interrupt Enable
ED_INTSRC: Interrupt Source Register
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W Register
R Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
005Dh
005Eh
005Fh
0060h
SERVO
SV_Servo_CR: Servo Control Register
SV_TWC_CR: Tracking Window Comparator CR
SV_TWC_CSR: TWC Control/Status Register
FS_CR: Focus Search Control Register
00h
00h
00h
00h
R/W Register
R/W Register
R/W Register
R/W Register
0061h
0062h
Not Available
0063h
0064h
0065h
0066h
0067h
SPDIF
Interface
CRSR: Status Register
CSLO: Left Channel, LSBs
CSL1: Left Channedl, MSBs
CSR0: Right Channel, LSBs
CSR1: Right Channel, MSBs
00h
00h
00h
00h
00h
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
Address
Block
Register name
Reset
Status
Remarks
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