參數(shù)資料
型號(hào): TDA7503
廠商: 意法半導(dǎo)體
英文描述: DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS
中文描述: 雙DSP普樂士微音頻應(yīng)用
文件頁(yè)數(shù): 3/26頁(yè)
文件大小: 182K
代理商: TDA7503
PIN DESCRIPTION
N.
Name
Type
Reset
Status (1)
Function
11
LRCKR
I
Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select
signal for received serial audio data. This signal has a frequency equal to
the audio sample rate.
Audio Serial Port Receive Bit Clock. SCLK clocks receiveddigital audio
data into pins SDI0, SDI1, SDI2, and SDI3
StereoDigital Audio Data. SDI0 is a stereo digital audio datainput pin
channel 0.
StereoDigital Audio Data. SDI1 is a stereo digital audio datainput pin
channel 1.
StereoDigital Audio Data. SDI2 is a stereo digital audio datainput pin
channel 2.
Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital
audio datainput pinand is multiplexed with the SSI’s Serial Receive
Data Input channel 3.
Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The
Left/Right select signal for transmitted serial audio data. This signal has a
frequency equal to the audio sample rate. This signal is multiplexed with
the SSI’s Frame Sync Input.
Audio Serial Port Transmit Bit Clock/SSI Serial Bit Clock. SCLK clocks
digital audio dataout of pins SDO0, SDO1, SD02, SD03, and SD04. This
pin is multiplexed with the SSI’s serial bit clock.
StereoDigital Audio Data. SDO0isa stereodigitalaudiodataoutput pin
channel 0.
StereoDigital Audio Data. SDO1isa stereodigitalaudiodataoutput pin
channel 1.
StereoDigital Audio Data. SDO2isa stereodigitalaudiodataoutput pin
channel 2.
StereoDigital Audio Data. SDO3isa stereodigitalaudiodataoutput pin
channel 3.
Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital
audio dataoutput pin and is multiplexed with the SSI’s Serial Transmit
Data Output channel4.
SCAN Enable. Enable SCANPath andMUXing of SCANIN and SCANOUT
Pins.
Test Enable. Enable Scan Mode Clocks. An active low signal will enable
the same clock to all scan chains. This pin also makes all latches
transparent.
DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line
0.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 0. When in DRAM Mode they act as the EMI dataline 0.
DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line
1.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 1. When in DRAM Mode they act as the EMI dataline 1.
DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line
2.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 2. When in DRAM Mode they act as the EMI dataline 2.
DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line
3.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 3. When in DRAM Mode they act as the EMI dataline 3.
DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line
0. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 4. When in DRAM Mode they act as the EMI address line 0.
12
SCLKR
I
16
SDI0
I
15
SDI1
I
14
SDI2
I
13
SDI3
I
25
LRCKT
I
24
SCLKT
I
21
SDO0
O
High
20
SDO1
O
High
19
SDO2
O
High
18
SDO3
O
High
17
SDO4
O
High
34
SCANEN
I
33
TESTEN
I
49
SRA_D0/DRD0
I/O
I
48
SRA_D1/DRD1
I/O
I
47
SRA_D2/DRD2
I/O
I
46
SRA_D3/DRD3
I/O
I
43
SRA_D4/DRA0
I/O
O, High
TDA7503
3/26
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