參數(shù)資料
型號： TDA7503
廠商： 意法半導(dǎo)體
英文描述： DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS
中文描述： 雙DSP普樂士微音頻應(yīng)用
文件頁數(shù)： 12/26頁
文件大?。?/td> 182K
代理商： TDA7503
Five Word Packet
DataWord
FrameSync 1
FrameSync 0
Data In
SCK
Receive
Interrupts
NETWORK MODE
FrameSync 1
FrameSync 0
Data In
SCK
Receive
Interrupts
NORMAL MODE
Figure 7. SSI Protocol.
The timing diagrams for the SSI Interface are
shown in Figure 7 for both Network and Normal
modes.
In Normal Mode the rising edge FSYNC startsthe
internal bit counter to allow data to be clocked in
or out. When bit count is equal to the pro-
grammed word length the counter is reset and
the shift registeris broadside loaded into the data
register. Additional SCK pulses are ignored after
the counter is reset. The next word is clocked in
or out starting with the next rising edge of
FSYNC.
In Network Mode the rising edge FSYNC starts
the internal bit counter to allow data to be clocked
in or out. When bit count is equal to the pro-
grammed word length the counter is reset and
the shift register is broadsideloaded into the data
register. At this point the FSRSD bit is set indicat-
ing that a frame sync was received with that
word. After being reset the counter continues
counting, clocking in the next word. Only when
the next rising edge of FSYNC is detected is the
packet consideredcomplete.
TDA7503
12/26
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