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參數(shù)資料
| 型號(hào)： | TDA7319D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR |
| 中文描述： | 3波段數(shù)控音頻處理器 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | TDA7319D |
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SDA, SCL I
2
CBUSTIMING
Symbol
f
SCL
t
BUF
t
HD:STA
Parameter
Min.
0
Typ.
Max.
400
Unit
kHz
μ
s
μ
s
SCL clock frequency
Bus free time between a STOP and START condition
1.3
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
0.6
t
LOW
t
HIGH
t
SU:STA
t
HD:DA
t
SU:DAT
t
R
t
F
t
SU:STO
LOW period of the SCL clock
1.3
μ
s
μ
s
μ
s
μ
s
ns
HIGH periodof the SCL clock
0.6
Set-up time for a repeated START condition
0.6
Data hold time
0.300
Data set-up time
100
Rise time of both SDA and SCL signals
20
300
ns (*)
Fall time of both SDA and SCL signals
20
300
ns (*)
μ
s
Set-up time for STOP condition
0.6
All values referred to V
and V
levels
(*) Must be guaranteedby the I
C BUS master.
SDA
SCL
t
BUF
P
S
t
HD;STA
t
LOW
t
R
t
F
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
Sr
P
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
D95AU314
P = STOP
S = START
Definition of timing on the I
2
C-bus
TDA7319
8/16
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