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參數(shù)資料
| 型號： | TDA7319D |
| 廠商： | 意法半導體 |
| 英文描述： | 3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR |
| 中文描述： | 3波段數(shù)控音頻處理器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 169K |
| 代理商： | TDA7319D |
TimingDiagram of I
2
CBUS
DataValidity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must beexternally connected).
DataValidity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Startand Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop conditionis a LOW to HIGH tran-
sitionof the SDAline while SCLis HIGH.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. TheMSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAline is stableLOWduringthis clockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
TransmissionwithoutAcknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
μ
P can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the newdata.
This approach of course is less protected from
misworking and decreasesthe noise immunity.
Acknowledgeon the I
2
CBUS
TDA7319
7/16
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