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參數(shù)資料
| 型號(hào)： | TDA7313N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Digital Controlled Stereo Audio Processor with Loudness(數(shù)控立體聲音頻處理器) |
| 中文描述： | 數(shù)控立體聲音頻處理器響度（數(shù)控立體聲音頻處理器） |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | TDA7313N |
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I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7313N and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 17, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop Conditions
As shown in fig.18 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferredon the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 19). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineis stableLOWduringthisclockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
μ
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreasesthe noise immunity.
Figure 17:
Data Validity on the I
2
CBUS
Figure16:
TypicalTone Response(with the ext.
components indicatedin the test
circuit)
Figure 15:
Bass Resistancevs. Temperature
TDA7313N
8/14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA7313ND | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS |
| TDA7314 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESS |
| TDA7315 | 功能描述:音頻 DSP Digital Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TDA7315D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED AUDIO PROCESSOR |
| TDA7316 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FOUR BANDSDIGITAL CONTROLLED GRAPHIC EQUALIZER |
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